DP83867CR: 10Base-Te MAU test

Hi Masakazu-san,

Please let allow me time to discuss with team to see what SW/HW adjustments can be made to tune performance for this.

I should have feedback for you by Wednesday 4/3.

Thank you,

Evan

Hello Evan-san,

Thank you for your support.

The customer had a discussion with the measurement instrument maker and they advised him to reduce the Tx equalizer strength and increase the DC gain as shown in the waveform below to see if there is a possibility of flattening. does setting 0x0E81 as described in 8.6.47 seem to have any effect? Attached is a capture of the test environment.

Regards,

Masakazu Adachi

Hi Masakazu-san,

Thank you for sharing the details for the setup.

Can the test be repeated with the Link Partner (PC) removed? There may be crosstalk from this. Also, is the 100ohm load populated during the test?

For now, I'd like to focus on confirming the layout before making software adjustments. Is it possible to share the layout checklist file filled out in the previous E2E thread?

Best regards,

Evan

Hello Evan-san,

The customer will try to removed the Link Partner (PC). He said the test results will be sent later. Also, they used 100ohm resister.

I shared layout checklist. 

2251.SLVRBN1_ DP83867_Design_Review_Checklist.xlsx

The difference in the Layout check list was Signal Routing. There were some areas where 30 mils were not taken.

Regards,

Masakazu Adachi

Hi Masakazu-san,

Thanks for sharing the details, curious to see the results when the customer is able to send.

For tuning gain, please use register 0x00A0[4:0]. These four bits increment the gain in 4% steps ('1000' = 0% change, can be incremented in + or - steps).

Best regards,

Evan

Hello Evan-san,

[1] I have received the results of the test with the link pattern removed from the customer and am attaching them.

Link Partner removed.pdf

[2] I could not find 0x00A0[4:0] in the datasheet, where is it listed? Also, am I correct in assuming that the default is 1000=0?

[3] Is it likely to be useful to set the register 0x0E81 described in "8.6.51 DSP Feedforward Equalizer Configuration" in the customer's configuration?

Regards,

Masakazu Adachi

Hi Masakazu-san,

[1] Thanks for sharing. It does not look like there is significant cross-talk from the link partner, so we can focus on tuning the gain.

[2] This is an internal register, please refer to the register description I shared above. You are correct, '1000' = 0% gain, adjust in positive or negative increments for 4% steps in gain.

[3] This register may also improve performance, but please test with only one register adjusted at a time.

What is the stage of the customer's design? I would like to show passing result with register configuration for current HW, however is the customer open to layout redesign to improve performance as well?

Thank you,

Evan

Hello Evan-san,

They were able to pass the test by adjusting the gain. They also informed us that it is difficult to change the pattern because of the upcoming release.
I received two questions from the customer, could you please confirm them?

[1] Register 0x00A0[4:0] has 5 bits, is '01000' = 0% the default?
The customer thinks that 07h = '00111' default from the test results.
[2] Based on the attached results, the customer is considering setting register 0x00A0[4:0] to '0x070Ah' or '0x070Bh'. Does this change affect the signal quality of 1000Base or 100Base?

Regards,

Masakazu Adachi

Hi Masakuzu-san,

[1] The default will change from PHY to PHY, trimmed during manufacturing/test.

[2] We expect DP83867 to pass 10Base-Te MAU compliance without this register configuration, so I would like to review layout & schematic to see if there are any adjustments that can be made without relying on extra register configuration during production. Although this register config is working in this case, I am worried about PHY-to-PHY marginality.

Please share the layout and schematic with me (e-mayhew@ti.com for private share).

Thank you,

Evan

Hello Evan-san,

I will request the customer if the layout can be shared.

Also,  Could you please check the following question about 0x00A0[4:0]?

[1] Register 0x00A0[4:0] has 5 bits, is '01000' = 0% correct? I received the following answer previously, so I am checking again.

Evan Mayhew said:

You are correct, '1000' = 0% gain, adjust in positive or negative increments for 4% steps in gain.

[2] I understand that the default is different for each PHY, so the customer's read was 07h = '00111', does this mean that the gain of this device was adjusted to 00111?

Regards,

Masakazu Adachi

Hi Masakuzu-san

Thank you, I can review and provide suggestions after sharing.

[1] This is correct, '01000' = 0% gain.

[2] Yes, if the default value after booting is '00111', this was adjusted during the manufacturing process.

Thank you,

Evan