SN65DSI84: Low LVDS clock frequency & PLL lock problem

Shaswath TS

Part Number: SN65DSI84
Other Parts Discussed in Thread: SN65DSI85

Hello,

We are using SN65DSI84 to convert from DSI to LVDS on our custom i.MX8MP board.

We used the DSI tunner to obtain the values for CSR registers, Our requirement is single channel DSI to single link LVDS (with 1 Clock & 4 Data lane), 24 BPP, and RGB888 Format. Instead of pannel we have an FPGA, i.MX8MP -> SN65DSI84 -> FPGA.

The issue is blank screen with some noise and we notice that LVDS clock frequency is very low (12.4MHz) when probed using oscilloscope instead of (actual 74.5MHz) and the PLL status bit in register 0x0A keeps changing, increasing the wait time for PLL lock did not work.

root@:~$ i2cget -f -y 1 0x2c 0x0a
0x8b
root@:~$ i2cget -f -y 1 0x2c 0x0a
0x0b
root@:~$ i2cget -f -y 1 0x2c 0x0a
0x8b
root@:~$ i2cget -f -y 1 0x2c 0x0a
0x0b

We need 1920x1080 resolution at 30 FPS at the bridge output & the timing info are mentioned below and also please find the attached screenshot of DSI tunner inputs.

Horizontal Timings:

HFP 88

HPW 44,

HBP 148,

Blanking Total 280,

Total Pixels 2200

Vertical Timings:

VFP 4,

VPW 5,

VBP 36,

Blanking Total 45

Total Lines 1125

Thanks & regards,

Shaswath

over 1 year ago

0 Vishesh Pithadiya over 1 year ago

TI__Mastermind 45771 points

Hey Shaswath,

Have you been able to get the color bar to work correctly?

If possible try connecting a video panel with the same spec.

0 Shaswath TS over 1 year ago in reply to Vishesh Pithadiya

Prodigy 10 points

I was unable to get the test pattern working.

Yes we have tested this on another i.MX8MP board in which we use SN65DSI85 (i.MX -> DSI85 -> Panel) and it works well with the same configuration.

0 Vishesh Pithadiya over 1 year ago in reply to Shaswath TS

TI__Mastermind 45771 points

Hey Shaswath,

Tis could bee a termination issue at the output because of FPGA. The DSI84 and DSI85 should be pin to pin compatible. Are you able to test the DSI84 chip on the DSI85 board? It seems that you are using the right tools and setup, but Imp not sure why one works and the other doesn't if the configuration is the same. Can you capture waveforms at the LVDS outputs for the working board and non-functional board?

0 Shaswath TS over 1 year ago in reply to Vishesh Pithadiya

Prodigy 10 points

No swapping the chips are not possible, I will get some clarification regarding the termination at FPGA and also try to get back to you with the waveform next week.

0 Shaswath TS over 1 year ago in reply to Shaswath TS

Prodigy 10 points

Hello Vishesh,

Sorry for the delayed response.

As per your suggestion there was format mismatch between the bridge & FPGA. After resolving the issue we got the test pattern working but with an external refclk source and now I want to use the DSI data lanes to output something while keeping this external clock as it is but the screen just flicker.

0 Vishesh Pithadiya over 1 year ago in reply to Shaswath TS

TI__Mastermind 45771 points

Hey Shaswath,

Good to hear that you have the color bar working. Here is a snippet from the flickering video debugging guide that is relevant to where you are in testing.

Summary: When the color bar works and the DSI inputs don't, this means that there is an issue with the timing of your signals, please verify this as seen in the image above. Additionally, Please double check signal integrity and verify that the timing registers are the same for DSI inputs and the color bar.

the

Full Guide: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/990480/faq-sn65dsi84-how-to-debug-flickering-video-with-sn65dsi83-sn65dsi84-and-sn65dsi85?tisearch=e2e-sitesearch&keymatch=sn65dsi84#

0 Shaswath TS over 1 year ago in reply to Vishesh Pithadiya

Prodigy 10 points

Hello Vishesh,

Thanks for the guide!

There was an interchange in connection between DSI clock and a data pair, after correcting them I am able to get the test pattern using the DSI clock source which is good, but when the test pattern is switched off we see the flickering and at this point I used the DSI tunner tool to double check the configuration from i.MX and the register values configured into the DSI84 chip. The values are is indeed what I am expecting them to be but the DSI clock on the scope is not correct.

I have attached the register dump of DSI84, DSI config from i.MX & the CSR list from the DSI-Tunner:

i2cdump -f -y 1 0x2c

No size specified (using byte-data access)
     0 1 2 3 4 5 6 7 8 9 a b c d e f    0123456789abcdef
00: 35 38 49 53 44 20 20 20 01 00 0b 10 00 01 00 00    58ISD   ?.??.?..
10: 26 00 59 00 00 00 00 00 78 00 03 00 00 00 00 00    &.Y.....x.?.....
20: 80 07 00 00 38 04 00 00 21 00 00 00 2c 00 00 00    ??..8?..!...,...
30: 05 00 00 00 94 00 24 00 58 00 04 00 00 00 00 00    ?...?.$.X.?.....
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 79 00 00 00 00 00 00 00 00 00 00    .....y..........
f0: 00 00 00 00 40 00 00 80 00 00 00 00 00 00 00 00    ....@..?.......

Fullscreen imx-drm-config.txt Download

root@:~$ modetest -M imx-drm
Encoders:
id      crtc    type    possible crtcs  possible clones
40      33      DSI     0x00000001      0x00000001
42      0       TMDS    0x00000004      0x00000002

Connectors:
id      encoder status          name            size (mm)       modes   encoders
41      40      connected       DSI-1           169x104         1       40
  modes:
        index name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot
  #0 1920x1080 60.00 1920 2008 2052 2200 1080 1084 1089 1125 148500 flags: nhsync, nvsync; type: preferred, driver
  props:
        1 EDID:
                flags: immutable blob
                blobs:

                value:
        2 DPMS:
                flags: enum
                enums: On=0 Standby=1 Suspend=2 Off=3
                value: 0
        5 link-status:
                flags: enum
                enums: Good=0 Bad=1
                value: 0
        6 non-desktop:
                flags: immutable range
                values: 0 1
                value: 0
        4 TILE:
                flags: immutable blob
                blobs:

                value:
43      0       disconnected    HDMI-A-1        0x0             0       42
  props:
        1 EDID:
                flags: immutable blob
                blobs:

                value:
        2 DPMS:
                flags: enum
                enums: On=0 Standby=1 Suspend=2 Off=3
                value: 0
        5 link-status:
                flags: enum
                enums: Good=0 Bad=1
                value: 0
        6 non-desktop:
                flags: immutable range
                values: 0 1
                value: 0
        4 TILE:
                flags: immutable blob
                blobs:

                value:
        44 max bpc:
                flags: range
                values: 8 16
                value: 0

CRTCs:
id      fb      pos     size
33      46      (0,0)   (1920x1080)
  #0 1920x1080 60.00 1920 2008 2052 2200 1080 1084 1089 1125 148500 flags: nhsync, nvsync; type: preferred, driver
  props:
        24 VRR_ENABLED:
                flags: range
                values: 0 1
                value: 0
36      0       (0,0)   (0x0)
  #0  nan 0 0 0 0 0 0 0 0 0 flags: ; type: 
  props:
        24 VRR_ENABLED:
                flags: range
                values: 0 1
                value: 0
39      0       (0,0)   (0x0)
  #0  nan 0 0 0 0 0 0 0 0 0 flags: ; type: 
  props:
        24 VRR_ENABLED:
                flags: range
                values: 0 1
                value: 0

Planes:
id      crtc    fb      CRTC x,y        x,y     gamma size      possible crtcs
31      33      46      0,0             0,0     0               0x00000001
  formats: XR24 AR24 RG16 XB24 AB24 AR15 XR15
  props:
        8 type:
                flags: immutable enum
                enums: Overlay=0 Primary=1 Cursor=2
                value: 1
        32 zpos:
                flags: immutable range
                values: 0 0
                value: 0
34      0       0       0,0             0,0     0               0x00000002
  formats: XR24 AR24 RG16 XB24 AB24 AR15 XR15
  props:
        8 type:
                flags: immutable enum
                enums: Overlay=0 Primary=1 Cursor=2
                value: 1
        35 zpos:
                flags: immutable range
                values: 0 0
                value: 0
37      0       0       0,0             0,0     0               0x00000004
  formats: XR24 AR24 RG16 XB24 AB24 AR15 XR15
  props:
        8 type:
                flags: immutable enum
                enums: Overlay=0 Primary=1 Cursor=2
                value: 1
        38 zpos:
                flags: immutable range
                values: 0 0
                value: 0

Frame buffers:
id      size    pitch

root@:~$

Fullscreen SN65DSI84_CSR.txt Download

//=====================================================================
// Filename   : SN65DSI84_CSR.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
0x09              0x00
0x0A              0x0b
0x0B              0x10
0x0D              0x00
0x10              0x26
0x11              0x00
0x12              0x59
0x13              0x00
0x18              0x78
0x19              0x00
0x1A              0x03
0x1B              0x00
0x20              0x80
0x21              0x07
0x22              0x00
0x23              0x00
0x24              0x00
0x25              0x00
0x26              0x00
0x27              0x00
0x28              0x21
0x29              0x00
0x2A              0x00
0x2B              0x00
0x2C              0x2c
0x2D              0x00
0x2E              0x00
0x2F              0x00
0x30              0x05
0x31              0x00
0x32              0x00
0x33              0x00
0x34              0x94
0x35              0x00
0x36              0x00
0x37              0x00
0x38              0x00
0x39              0x00
0x3A              0x00
0x3B              0x00
0x3C              0x00
0x3D              0x00
0x3E              0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

0 Vishesh Pithadiya over 1 year ago in reply to Shaswath TS

TI__Mastermind 45771 points

Are you able to probe the DSI lanes and verify the line time?

It seems that the color bar is working with the DSI clock just fine, so there isn't any reason the DSI clock should change when you toggle the color bar. What changes do you make in your script between going from color bar to DSI data?

0 Vishesh Pithadiya over 1 year ago in reply to Vishesh Pithadiya

TI__Mastermind 45771 points

Looking at your register sittings (DSI84 CSR) and your register dump, the following circled bits are mismatched.

I cannot support you in the i.MX configuration as it is outside my scope of expertise.

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SN65DSI84: Low LVDS clock frequency & PLL lock problem