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[FAQ] SN75DPHY440SS: Is it okay to swap the polarity and lane order?

David (ASIC) Liu
Guru*** 149685 points
Part Number: SN75DPHY440SS

My customer asked about changing positive signal and negative signal.

(i.e. applying positive input to DA0N, negative input to DA0P, positive input to DA1N, negative signal to DA1P, and so on.)

Is it okay to use this device like this and Is this fully operational?

Is it okay to swap the lane as well?

  • 0
    TI__Guru*** 149685 points

    For polarity swap

    The DPHY440 can't support polarity inversion, the above proposal will not work in DPHY440 default state. The high speed entry sequence consists of driving LP11->LP01->LP00 (LP->HS transition). If you flip the polarity, then the high speed entry sequence will be flipped as well and you will never able to enter into HS mode. 

    The only way it will work is that if the DPHY440 is in I2C mode and only HS mode is always enabled using the following sequence. The sequence puts the CLK and all data lanes into HS mode only.

    Write Register 0x50 with 8’h1F //Override enable for HS TX path

    Write Register 0x51 with 8’h1F //HS TX path enabled.

    Write Register 0x61 with 8’h00  // Disable LP path.

    Write Register 0x70 with 8’h1F  //Override enable for HS RX path

    Write Register 0x71 with 8’h1F  // HS RX path enabled

    For lane swap

    It depends on whether this is a DSI or a CSI-2 application.

    For DSI

    One of the four lanes is used for back channel communications between GPU and DSI panel. DPHY440’s lane 0 is the only lane that supports the back channel. For this reason, DPHY440 lane 0 must always be connected to lane 0 of GPU and panel. Other lanes can be swapped as long as the lane order is maintained between the DPHY440 input and the output.

    For CSI-2

    The DPHY440 supports 4 CSI-2 DPHY lanes plus a clock. Unlike DSI, CSI-2 does not have a back channel path. Because of this, there is no requirement on lane ordering. Because there is no lane ordering requirement, there are more combinations which can be implemented. All possible combinations are supported by the DPHY440 as long as the lane order is maintained between the DPHY440 input and the output.

    Please note that lane 0 is a special lane. 

    DPHY440’s LP TX is expecting to connect to an unterminated LP RX.  With Lane 0 path (DA0P/N and DB0P/N) supporting bi-directional LP signaling, it is very important that DB0P/N LP TX is connected to an unterminated LP RX.  If DB0P/N LP TX is connected to a HS RX, then LP signaling will not be able to reach the LP11 levels and which will cause the DPHY440 to not enable HS data path on Lane0.

    Try following for enabling lane0 HS path:

    Enable HS path for Lane 0 only:

    Write Register 0x50 with 8’h01 //Override enable for HS TX path

    Write Register 0x51 with 8’h01 //HS TX path enabled

    Write Register 0x61 with 8’h00  // Disable LP path

    Write Register 0x70 with 8’h01  //Override enable for HS RX path

    Write Register 0x71 with 8’h01  // HS RX path enabled

    Thanks

    David