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TCAN4551-Q1: Rx FIFO 0 Status reports with reserve bits set

G T
Expert 1940 points
Part Number: TCAN4551-Q1

Hello!

I am seeing that after running for sometime, Rx FIFO0 status register shows RX FIFO0 full status.

To see exactly what is going on, I started reading the FIFO0 status register every 1 second and I noticed that just before setting FIFO0 full status, the status register read shows 0x88000000. From the datasheet, these are reserved bits. Also once this shows up, the successive reads of FIFO0 status shows that the fill index keeps increasing without generating watermark interrupt and eventually end up in FIFO0 Full status but set.

To add some context, I am using tcan4551 in test mode with an external transceiver via TXD and RXD connections. I also have some filters, xid filters are enabled. sid filters are not being used, so I had SIDNumElements set to 0.
Things seem to be working as expected until I hit this case and then the whole communication is halted.

Any pointers on what those bits are, and why they are getting set? Any other ideas on debugging?

Thanks!
GT

  • 0
    TI__Guru 74262 points

    GT,

    Our expert has been assigned this thread and is checking on this for you. Please give us until Monday next to get back to you with a reply.

    Regards,

    Eric Hackett 

  • 0
    TI__Guru 53555 points

    Hi GT,

    I'm sorry you're having this issue. Let me ask for a bit more information to help recommend a possible solution here. 

    • Can you share how your filter configuration (SFEC) is set, particularly to confirm that the filter is configured to place new messages into the correct FIFO that is being checked by the MCU. 
    • Please confirm the MRAM configuration accounts for the full memory allocated to FIFO 0 and the subsequent start address in RAM for other elements does not overlap with the required allocation for the FIFO when full. 
    • Ensure that the MCU is properly acknowledging the reads from the FIFO so that the memory is cleared for use. 

    For the apparently invalid status register read value here, I would like to confirm that the SPI for this system is working correctly. You state that other functions are working properly during the test so I don't doubt that the information is being handled correctly between the MCU and controller. However I would like to check this read on a logic analyser or oscilloscope to see what the MOSI is driving to the device and confirm the device response on MISO. Would it be possible to capture this transaction?

    Regards, 
    Eric Schott

  • 0 in reply to Eric Schott1
    Expert 1940 points

    After debugging some more, I figured out that I had a SPI error show up, before the FIFO starts filling up. I fixed the SPI error and things are looking stable now. Thanks for the response. This is resolved now.