The figure below is an excerpt from Figure 10 on page 11 of the SN65LVDS93A Data sheet.
This figure shows CLKIN and CLKOUT with CLKSEL = High level condition.
However, based on actual measurements, CLKSEL=Low level seems to be the correct condition.
" CLKSEL at high level" is correct?
Hi, the Yn "period" beginning with the first bit at t0 starts when CLKOUT has a rising edge. 
And rising edge is selected when CLKSEL is high according to the datasheet.
The CLKIN and CLKOUT delay is shown in as t7 at the top.
However, based on actual measurements, CLKSEL=Low level seems to be the correct condition
Is there anything different you found in your measurements? If so, could you show us the waveforms in logic analyzer captures?
Best regards,
Ikram
