Hi Sir:
It will be used in PCIe 5.0 CLOCK 100MHz design, which can meet PCIE 5.0 delay time (what's the delay time in the 1:2 or 2:1 design?) and phase jitter needs?
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Hi Sir:
It will be used in PCIe 5.0 CLOCK 100MHz design, which can meet PCIE 5.0 delay time (what's the delay time in the 1:2 or 2:1 design?) and phase jitter needs?
Hi Chenqi:
Delay time for TMUXHS4212 is 70ps, What is spec for PCIE 5.0 delay time?
Regards
Brian