DP83867IR: How to set Tx/Rx delay time at RGMII 100MHz

Hi Atsushi-san,

May I ask what is the trace length different between the CLK and Data signals?

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Regards,

Hillman Lin

Hi Hillman-san,

Thank you for your reply.

Please allow me confirm the background of your question.

Does it mean that delays of more than 4ns need to be adjusted with the trace length, it cannot be adjusted with the register?

Hi Hillman-san,

Thank you for your reply.

I'd like to confirm, just in case.

Is the programmable maximum delay 4ns even when using at 100Mbps?

I think this register table assumes 10Mbps.

Because the default value 2ns(0111b) corresponds to 90℃ delay of GTX clock 125MHz.

Hi Atsushi-san,

Sorry for the confusion. I discuss with the team internally.

We have two mode to that can tune the setup and hold time: 

• Register 0x0032 provide 90 degree phase shift between clock and data
• Register 0x0068 provide fix delay and independence with the speed between clock and data

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Regards,

Hillman Lin

Hi Hillman-san,

I think register 0x0032 [1]=1b/[0]=1b are shift mode and [1]=0b/[0]=0b are aligned mode.
Is my understanding correct below?

- The shift mode always provides 90 degree shift no matter what speed, 10Mbps/100Mbps/1000Mbps, they are using.
In this case, setting value of register 0x0086 is ignored.

- The aligned mode provides delay time set in register 0x0086.

Hi Atsushi-san,

Your understanding is correct.

• 0x0032[1] is for TX shift and align mode
• 0x0032[0] is for RX shift and align mode.

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Regards,

Hillman Lin