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DS90UB948-Q1: I2S data cannot be transmitted by bit clock frequency

Shinichi Inoue
Guru 21971 points
Part Number: DS90UB948-Q1
Other Parts Discussed in Thread: TAS2505, , DS90UB925Q-Q1

Dear Specialists,

My customer is considering  SER (DS90UB925) and Des (DS90UB948) and has a question.

I would be grateful if you could advise.?

---

I2S data from the I2S master to audio amp(TAS2505) via SER (DS90UB925) and Des (DS90UB948).
Data bits are 16 bits.

When the bit clock is lowered, 2kHz audio cannot be played.

situation
(1) To play a 2kHz pure tone with TAS2505,
When I sent sine wave data from the I2S master to TAS2505 at LR CLOCK8kHz, I could not play the sound.

(2) When I raised the BIT CLK and set the LR CLOCK to 32kHz, I was able to get the desired sound up to 1kHz, but the sound was different above that.

(3) By further increasing BIT CLK and setting LR CLOCK to 64kHz, it is now possible to play up to 2kHz.

question

(1) The sound cannot be played unless it is transmitted with an LR CLOCK that is at least 32 times the frequency you want to play.
Is there a setting error in SER(DS90UB925) Des(DS90UB948)?

(2) Regarding DS90UB948, the Des register “7.7.1.49 I2S_DIVSEL Register (Address =0x3A)”,
When used with the reset value (0x0), will the clock input to serializer be output from Des as is?
Please let me know how it is converted.

(3) Is there a relationship that should be observed between I2S bit CLK, I2S CLK, PCLK (Serializer) and MCLK (De-serializer)?

---

I appreciate your great help in advance.

Best regards,

Shinichi

  • 0
    TI__Mastermind 25765 points

    Hi Shinichi,

    Thanks for your questions. I will get back to you on Monday, apologies for the delay.

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    TI__Mastermind 25765 points

    Hi Shinichi,

    Can you let me know what the I2S frequency is?

    Shinichi Inoue said:
    (3) Is there a relationship that should be observed between I2S bit CLK, I2S CLK, PCLK (Serializer) and MCLK (De-serializer)?

    For the DES, the bit clock (I2S_CLK) supports frequencies between 1 MHz and the smaller of < PCLK/2 or < 13 MHz. For the SER, see the table below:

    I am still looking into you other question.

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Guru 21971 points

    Hi Ben,

    Thank you for your reply.

    The customer has additional questions.

    Could you please advise?

    ---

    (1)About the deserializer ds90ub948-q1
    >Bit clock (I2S_CLK) must be between 1MHz and PCLK/2 or <13MHz.

    Is it recognized that the clock input to Ser's PCLK becomes Des' PCLK as is?

    In that case, since the Ser PCLK input is giving 74.25MHz, the upper limit clock is 13MHz, which is smaller than PCLK/2.
    In other words, is it correct to understand that the bit clock can be in the range of 1MHz < I2S_CLK < 13MHz?

    (2)About serializer ds90ub925q-q1
    "Table 3. Audio Interface Frequencies" Are only the combinations listed in this table compatible with input?
    Or do you just list typical combinations within the usable range?

    Is DATA WORD SIZE(16/24) correct based on the number of bits of each, not the L/R combination?

    (3)Does this mean that it cannot be used under the following conditions?
    I2S CLK=2.074MHz
    DATA WORD SIZE is 16bits (L/R total 32bits)
    SAMPLE RATE is 66.368kHz 1/(1/2.074MHz * 16bits * 2)

    ---

    I appreciate your great help and cooperation.

    Best regards,

    Shinichi

  • +1 in reply to Shinichi Inoue
    TI__Mastermind 25765 points

    Hi Shinichi,

    Shinichi Inoue said:

    (1)About the deserializer ds90ub948-q1
    >Bit clock (I2S_CLK) must be between 1MHz and PCLK/2 or <13MHz.

    Is it recognized that the clock input to Ser's PCLK becomes Des' PCLK as is?

    In that case, since the Ser PCLK input is giving 74.25MHz, the upper limit clock is 13MHz, which is smaller than PCLK/2.
    In other words, is it correct to understand that the bit clock can be in the range of 1MHz < I2S_CLK < 13MHz?

    Correct.

    Shinichi Inoue said:

    (2)About serializer ds90ub925q-q1
    "Table 3. Audio Interface Frequencies" Are only the combinations listed in this table compatible with input?
    Or do you just list typical combinations within the usable range?

    Is DATA WORD SIZE(16/24) correct based on the number of bits of each, not the L/R combination?

    (3)Does this mean that it cannot be used under the following conditions?
    I2S CLK=2.074MHz
    DATA WORD SIZE is 16bits (L/R total 32bits)
    SAMPLE RATE is 66.368kHz 1/(1/2.074MHz * 16bits * 2)

    The table lists examples, but the values are all related to eachother. So the example in your #3 would work.

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Guru 21971 points

    Hi Ben,

    Thank you for your reply.

    I understand it could use for the customer's condition.

    I sent the information with the customer.

    I appreciate your great help and cooperation.

    Best regards,

    Shinichi