Dear Specialists,
My customer is considering TL16C2550 and has questions.
I would be grateful if you could advise.
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I would like to confirm th4 in figure 11. and th7 in figure 12. of the timing chart.
In our system configuration;
When writing is completed, /IOW goes High → 11ns, then address Hi-Z → /CSA goes High after 10ns.
Timing chart th4 “Hold time, address valid” = Min 10ns
We cannot meet the requirements, but will there be any problems?
Or is there no problem because /IOW is High first?
Regarding read, th7= Min 10ns is not satisfied because the chip select High is delayed by 10ns.
Is it acceptable for /CSx to go High after address HiZ?
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I appreciate your great help in advance.
Best regards,
Shinichi