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TL16C2550: Confirmation regarding th4 of Figure 11. and th7 of Figure 12.

Part Number: TL16C2550

Dear Specialists,

My customer is considering TL16C2550 and has questions.

I would be grateful if you could advise.

ーーー

I would like to confirm th4 in figure 11. and th7 in figure 12. of the timing chart.


In our system configuration;

When writing is completed, /IOW goes High → 11ns, then address Hi-Z → /CSA goes High after 10ns.

Timing chart th4 “Hold time, address valid” = Min 10ns

We cannot meet the requirements, but will there be any problems?

Or is there no problem because /IOW is High first?

Regarding read, th7= Min 10ns is not satisfied because the chip select High is delayed by 10ns.

Is it acceptable for /CSx to go High after address HiZ?

 Timing Chart.tif

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I appreciate your great help in advance.

Best regards,

Shinichi

  • We cannot meet the requirements, but will there be any problems?

    Or is there no problem because /IOW is High first?

    This should be fine, Since #IOW is going high the other signals can transition later. The device itself doesn't start clocking in data until #IOW is low. 

    Regarding read, th7= Min 10ns is not satisfied because the chip select High is delayed by 10ns.

    Is it acceptable for /CSx to go High after address HiZ?

    Yes. When writing to UART devices it's more important to set the other input pins (D0-D7, CS, A0-A2, ect..) and then toggle #IOW low last. Once #IOW goes high, the other input pins can transition. The order isn't really important on the other input pins. All the sampling of the data occurs during the falling edge of #IOW.

    -Bobby

  • Hi Bobby,

    Thank you for your reply.

    I understand the customer's usage is acceptable.

    I'll share with the customer.

    When the customer has an additional question, I consult you again.

    I appreciate your great help and cooperation.

    Best regards,

    Shinichi