SN75LVDS83BDGG Compatibility

Hi Kent, there isn't enough information in the datasheet I found: http://www.thine.co.jp/products_e/LVDS/pdf/THC63LVDF84B_Rev.3.20_E.pdf

It needs to comply with the LVDS standard, TIA/EIA-644-A.  And it doesn't state its input common mode voltage range, or input differential voltage range, or whether there's integrated termination.

Based on its block diagram, there's a good chance it will work with the SN75LVDS83BDGG.  You also want to pay attention to the required serial bit order.  You may be able to find more information by viewing the datasheet of the LCD that has the THine receiver.

Thanks,
RE

Thank you for the response.  I have attached the LCD spec sheet link.

http://www.hedus.com/sales/uploads/TX14D10VM1BAA-2.pdf

Thank you.  I will let you know how well it interfaces when I receive the LCD.

I am using SN75LVDS83, CHMEI LVDS PANEL with CM1718A T-CON

and found that it looks not working with this LVDS Rx.

Can you provide any compatible LVDS Rx if you have?

I am using M185B1-LO2 Panel(Included CH1718A - LVDS Rx)

and using XGA VESA Standard Timing.

The Standard timings were probed correctly on Oscilloscope,

are there any evealution kits for testing of SNLVDS83 Tx or ercommand panels with LVDS Rx?

When I checked the default Panel Timing after LVDS Rx

the Horizontal : 37.74khz(STH), vertical : 46.79Hz(STV)

Thanks

openvideo, what is your LVDS clock frequency?  As for your Vsync frequency, I suggest you try 60Hz since that's much more common, even though the panel datasheet says it supports 40-75Hz.

To answer your question, we do have EVMs for LVDS transmitters and receivers.  If you used an RX board, it would convert the SN75LVDS83 data into CMOS parallel.  It sounds like you already have this ability, since you measured HSYNC and VSYNC.

Best regards,
RE

Hi

the XGA Timing is Pixel Clock - 65Mhz(15.4ns) ,Hysnc - 48.363 Khz(H), Vsync - 60.04 Hz(V).

I don't have 65Mhz VCO for now, So I am using 66.66Mhz to generate XGA signals, Hsync, DE, Vsync, Color Pattern Pixel Data

After SN75LVDS83, the Differential Signals looks fine, and the Panel Control Signals on the LVDS Rx(CH1718A, Chimei T-CON IC) looks fine.

But on the panel side, the STV, STH are coming out, but TP to dump horizontal Pixel, CPV which Horizontal Clock on the Panel is not coming,

so display is nothing.

Only different as compared with XGA standard timing is 66.66Mhz instead of 65Mhz(XGA Pixel Clock)

is it ok for SN75LVDS83 this clock?

Thanks

Yes, the SN75LVDS83 can be used at 66.66MHz, since it supports 31-68MHz.

So you are running at:
  PCLK = 66.66MHz
  Vsync = 60Hz
  Hsync = 48.363kHz

Your panel requires the horizontal time (Th) to be 1446-1936 cycles of Tc.  Tc = 1/66.66MHz = 15ns.  This indicates the required Hsync is 34.4kHz to 46.1kHz.  Try running in this range instead of 48.363kHz.

Best regards,
RE

The panel is with 1366(Active H) x 768(Active V) , 76Mhz, WVGA Maily

Th is 768 ~ 888 with 40 ~ 75Hz Frame, Tc is 1446 ~ 1936

55Mhz ~ 95Mhz, LVDS Clock.

I have 54Mhz, 66.66Mhz whci can work with SN75LVDS83 and this Panel.

The panel is only working with DE Mode.

Do you know the timing specification with 66.66Mhz or 54Mhz for WVGA?

Thanks

Your resolution is more commonly referred to as WXGA.  The timing spec is entirely defined by your panel datasheet, although VESA publishes their own recommendations.  VESA's DMT doc states 60Hz/47.7kHz/85.5MHz, and a reduced blanking of 60Hz/48kHz/72MHz.  You can also google "VESA CVT" for their Excel calculator.

Best regards,
RE

I got it.

I will try to make my onw timings withing the panel specification.

Thank you so much for your support

Regards

Open

By the way, do you have a EV Kit with LVDS Rx and any size panel for this SN75LVDS83 Testing?

There's an EVM that simply breaks out all the pins.  The CMOS side goes to a header, and the LVDS to SMA  The user needs to control every pin, and figure out how to interface to a panel.  Panels use different connectors.

Best regards,
RE

Here is LVDS Rx Specification(M185B1-L02 Panel), Vsync(40 ~ 75Hz), Hsync(1446 ~ 1936 pixel, 34.4kHz ~ 46.1Khz)

operation Clock( 50 ~ 95Mhz)

and  LVDS Tx Spcification(SN75LVDS83), operation Clock(31- 68MHz).

When I give the timing 41.96KHZ as DE(Hsync), the Panel T-CON generate the horizontal timing 20.98KHZ

No display , Due to several T-Con output control signal does not comes on related with horizontal timings.

Can you send the details on EVM to email ?

I would need to check if a SN75LVDS83 output is correct.

can you recommand a Panel which SN75LVDS83 tx works with?

I expect the SN75LVDS83 to work with all panels that comply with the LVDS standard (TIA/EIA-644).  The device is a simple serializer, and the output voltages comply with LVDS.  You might want to verify your bit mapping is correct.  I suspect the control of DE might not be correct for what the panel requires.  For EVM details, please email me at:  reisenbeis <at> ti <dotcom>.

Thanks,
RE