TFP410 not transmitting

Hi Mr. Doolittle,

I came across a document that describes errata for the TFP410 datasheet, and it includes that "MSEN = High" means a receiver is detected.  I don't know why the current datasheet doesn't have this fixed, but I will look into it.

http://www.ti.com/lit/er/sllz030a/sllz030a.pdf

So, maybe you could verify that MSEN is Low until the receiver is connected, and that it then goes High.  I believe at this point, there should be activity on the TMDS outputs.  Perhaps you could send me your schematic,  reisenbeis [at] ti [dot]com

Thanks,
RE

RossE,

Thanks for the errata link.  Yes I can verify that MSEN is low until the receiver is connected, then it goes high.  Schematics are sent.

Hi John, have you gotten any different results?  I haven't been able to find the problem yet.

Thanks,
RE

Nope, everything is still the same.  I have verified that NC is floating high and I have adjusted the DE signal timing between being always high and tracking HSYNC, all with the same results.

Hi John, sorry to hear this.  From what I understand, the TFP410 output TxC remains static High; our first goal should be to get the output clock.  Here are some more ideas:

1. Verify resistors R39, R33, and R30 are installed.
2. Measure the input clock on Pin 57, that it swings 0V-3V, and is 25-165MHz.
3. Do you have the ability to measure IDD?
4. If you have the ability, is IDD the same with and without the input clock IDCK running?

Thanks,
RE

RossE,

Yes the configuration resistors you mentioned are in place.  When a 50MHz wave is applied to +IDCK the current of both boards (TFP410 as well as the TFP403) jumps from 30mA to 70mA.  This is on a 5.0V rail, but it's both are using linear regulators, so that should be very close to the current pulled on the 3.0V VCCs of both chips.  Regardless of whether a clock is applied there is an output signal on the TFP403 receiver ODCK pin.  However, this output clock appears to have a random freq. and duty cycle, in no way does it represent what is going into the TFP410 +IDCK.  Also, the TXC+ and TXC- pins are continuously logic high even when the TFP403 is emitting this random ODCK signal.

Ross,

I found an OTS board that uses the TFP410 and built an adapter to pipe my imager signals into this board.  Then I connected it to my TFP403 board via HDMI cable.  This mostly worked however, I’m not using an actual DVI video source but rather an RGB camera sensor.  Generating that pesky DE signal to tell the TFP410 to transmit sync data is the sticking point I’m at now.  If I were to pursue the TFP410 approach I would have to develop a way to logic AND the active low HSYNC and VSYNC signals so that when either of them goes active DE also goes active.  I built a straight AND gate into my adapter board and the results are interesting.

First, the adapter rig correctly Txed almost all the signals and my TFP403 board Rxed them, which was reassuring.  The problem was that VSYNC worked fine but there was no output on the TFP403 for HSYNC.   I think that because my AND gate activated DE and HSYNC simultaneously the TFP410 didn’t start looking for a transition on HSYNC until after DE had gone low.  By that point HSYNC was already low and it was too late.  However VSYNCs always trail HSYNCs from my source and thus the TFP410 was able to detect those.

To the interesting part, what is the minimum delay time between DE and HSYNC?  The datasheet shows setup and hold times between the clock and data lines but not between data lines themselves.  Most likely, the HSYNC must wait at least one IDCK clock cycle after DE has been active before it can go active, is this true?

Hi Ross,

Did you have much success generating DE from VSYNC and HSYNC. Im trying to figure out a similar solution, as I only have those signals available.

steve

Hello Steve,

Could you please describe what is your requirement and/or current issue as well as your configuration?

Regards.

Hello,

Not sure if this is your issue or not, but I had the same problem with this chip, and it turns out that I had the 510 ohm resistor for TFADJ as a Pull-DOWN, not a PULL UP as required.  I changed it to a Pull up, and everything is working fine, up to 1920x1200 with reduced blanking.

Hope this helps you!

Jesse C.

Hi Folks,

I got my implementation going. Thanks all for your help. It turned out the timing of DE is critical. Modern monitors blank when the signal is not spot on, which dosent give you the opportunity to see if your "sort of" getting there. But it all worked really well in the end. Nice chip.

You can see the design here if your interested. I also posted the schematic and a few test screen snaps.

http://www.srkhdesigns.com/CBAVPB01.html

Steven, it's great to hear you worked through that.  And that's an interesting final product you have.

Best regards,
RE

Hi Steven,

With regards to the above discussion, I would like to put my concern also. My logic is also not working when I want to drive DVI Monitor.

In my schematics TVS410 is attached with FPGA in below configuration:
ISEL --> Pulled HIGH for I2C mode enabled
PD --> Grounded
IDCK- --> Grounded
IDCK+ --> 40Mhz clock

On startup;
Writing the default in CTL_1_MODE register; value=0xFE

Below is other register setup
-- --
DE_DLY --> H'64
DE_CTL --> H'30
DE_TOP --> H'4B
DE_CNT --> H'0320
DE_LIN --> H'0258
H-RES --> H'0384
V-RES --> H'02A3

After this I am reading the Values of above registers,
The read value are:
-- --
DVI DE_DLY = 0x64
DVI DE_CTL = 0x30
DVI DE_TOP = 0x4B

DVI DE_CNT Lower = 0x20
DVI DE_CNT Higher = 0x03

DVI DE_LIN Lower = 0x58
DVI DE_LIN Higher = 0x02

DVI H-RES Lower = 0x5E
DVI H-RES Higher = 0x03

DVI V-RES Lower = 0x67
DVI V-RES Higher = 0x02

After this writing value in CTL_1_MODE register; value=0xB5

Below is behaviour on Monitor attached with the board:
when FPGA programed, but register not configured --> Cable Not Connected
FPGA Programmed and register configured --> Blank screen

If I change some value of H-RES, DE_DLY, V-RES etc to some other value, Monitor shows --> data not supported.

I can attach the schematics of TVS410, wave forms of HSYNC, VSYNC, and DE. Please provide the email ID for the same.
In the data port I am giving some constant values.

Regards,

Chander

Hello

As per mentioned TADJ resistor to pull up and after that  chip is working fine..

I am using DELL Monitor (ST2220lb) & resolution is 1920X1080 60HZ.

Based on I 2c disable configuration setting and also TADJ resistor to pull up, I am sending RGB data at pixel clock @ 147.5 MHz, but I could not able to see display on monitor.

Kindly provide us your inputs.

Please provide your schematic for review.

Regards.