SN65DSI83: No picture with external REFCLK, test pattern okay, DSI clock okay

Hi,

Can you please share the LVDS panel spec? 

Thanks

David

I'm not allowed to share the document.

For 66.66 MHz, the timings for this panel calculate as follows:

clock-frequency = <66660000>;
hactive = <1024>;
vactive = <600>;
hsync-len = <44>;
hfront-porch = <160>;
hback-porch = <160>;
vfront-porch = <160>;
vback-porch = <23>;
vsync-len = <17>;
hsync-active = <0>; /* Active LOW */
vsync-active = <0>;
de-active = <1>; /* Active HIGH */
I am aware that for this particular panel, there are solutions within range of the DSI output, even as low as 50MHz, but I'm not interested in any solution that uses the DSI clock.

I'm using this panel to get the 83.33 -> 66.66 clock conversion to work on a "known good" system.

The real target is to get another panel working that has higher resolution so there's no solution below 62.5 MHz.

I forgot to ask the most important question: Is what we want even possible?

Can we get proper video output when the DSI clock and REFCLK are not related?

Hi,

LVDS_CLK = Htotal x Vtotal x frame rate = (1024+44+160+160) * (600+160+23+17) * 66.66 = 74.019264MHz

So the DSI_CLK = LVDS_CLK x bpp / 2 * DSI lanes. Assume bpp = 24, and DSI lanes = 4, DSI_CLK = 222MHz, which is still within the 40-500MHz DSI clock range, so the DSI83 can support this particular resolution.

Thanks

David

So it IS possible to use the DSI83 this way - using asynchronous DSI and REFCLK?

Then why doesn't it work?

Hi,

Can you please measure the line time on the DSI input and the LVDS output? The line time must match between the input and the output. The line time on the LVDS output is the total amount of horizontal pixels divided by the LVDS clock frequency.

Below is a scope waveform example

Thanks

David

Apparently my previous reply here was lost.

The issue here is that the DSI is incapable of generating "free" frequencies. It can only do a limited set of frequencies. There are two data lanes, so the DSI must run above 444MHz, the only solution being 500 MHz (hence a 500/6=83.33 MHz pixel clock)

We want to use a 33.33 MHz REFCLK to have a 66.66 MHz pixel clock. The DSI thus delivers 1735 pixels and the LVDS should output 1388 in the same timeframe.

I'll try to get my hands on equipment, may take a while because the DSI lanes aren't on accessible PCB layers. Please be patient.

The DSI outputs 1735 pixels at 83.33 MHz, so the line time is 1735/83.33 = 20.820 microseconds.

The LVDS should be outputting 1388 pixels at 66.66 MHz, so the line time is 1388 / 66.66 = 20.822 microseconds.

Hi,

For transmitting 1735 pixel on the DSI side, what is the actual active horizontal pixel?

Thanks

David

active pixels is 1024

What is the actual size of the line buffer in the sn65dsi83? Cannot find it anywhere in the datasheet.

Mike

The line buffer is around one active line, so it is important to keep the line time the same to avoid buffer overrun or underrun.

Thanks

David

So the line buffer can hold more than 1k pixels?

Mike

Yes, it will.

Thanks

David

Mike

I am closing this e2e thread due to inactivity, please reply back to this e2e thread if you have an update.

Thanks

David

We gave up on using an external clock, and just run the display out of spec.

For future users, it might be a good to put some instructions in the datasheet or create an application note detailing how the external clock is supposed to be used.