DS90UB9722-Q1: Power Sequence

d_zero

Genius 4775 points

Part Number: DS90UB9722-Q1
Other Parts Discussed in Thread: LM5141, TPS628503

Hi Team,

In DS SNLS657A ( DS90UB9722) on page 264 Table 10-1 it is stated:

" VDD18/VDDIO must come up before VDD11"

But it is not stated the min time when the VDD11 can start to rump-up, please can you provide this time requirement?

if used VDDIO is 3.3V is there any timing requirement between VDD18 = 1.8V and VDDIO = 3.3V ?

Can the VDDIO=3.3V come up before or after VDD18 ?

Best Regards,

over 1 year ago

0 Thomas Bejin over 1 year ago

TI__Mastermind 24751 points

Hi,

Thanks for reaching out with this question. In the case of the UB9722 power sequence we do not have a delay required between VDD18 and VDD11 rails. Only the requirement that VDD11 must reach 90% level after VDD18 is at 90% level.

In the case of VDDIO 3.3V, this should be brought up together with VDD18, before VDD11.

Best,.

Thomas

0 d_zero over 1 year ago in reply to Thomas Bejin

Genius 4775 points

Hi Thomas,

thank you for the replay.

In our case the 1.1V has a 3ms delay regarding to VDD18 , so this should be a problem from my understanding ?

but on the other hand in our case the VDDIO 3.3V rail or the PG from 3.3V converter will be connected to the EN of VDD18, is this a problem?

https://www.ti.com/lit/ug/snvu862/snvu862.pdf

https://www.ti.com/lit/an/slda060/slda060.pdf

LM5141 is generating VDDIO (3.3V) -> the PG from LM5141 is enabling LP87334E -> LP87334E LDO1 ( 1.8V) is enabling TPS628503 -> TPS628503 is generating VDD18 ( 1.8V)

Best Regards,

0 Thomas Bejin over 1 year ago in reply to d_zero

TI__Mastermind 24751 points

Hi,

Do you have a scope capture of this power-up sequence? I think I have a good understanding of what you're saying here but it would be helpful to have the background with rise times included as well.

d_zero said:
LM5141 is generating VDDIO (3.3V) -> the PG from LM5141 is enabling LP87334E -> LP87334E LDO1 ( 1.8V) is enabling TPS628503 -> TPS628503 is generating VDD18 ( 1.8V)

In the above quote you did not mention the VDD11 supply, how does the VDD11 rail fit in here?

Best,

Thomas

0 d_zero over 1 year ago in reply to Thomas Bejin

Genius 4775 points

Hi Thomas,

this is a new design, there is no PCB design at the moment.

The VDD11 is generated by LP87334E PMIC and will start ramping up 3ms after LP87334E enable, see Figure 3-1. LP87334E Power-up and Power Down Sequence in https://www.ti.com/lit/ug/snvu862/snvu862.pdf , while VDD18 (TPS628503 ) is enabled by 1.8V LDO1 LP87334E PMIC and LDO1 is ramping up 0ms after LP87334E enable, see Figure 4-1. AM68x Single LP87334E PDN-6K, Base Features Only in https://www.ti.com/lit/an/slda060/slda060.pdf

Best Regards,

0 Thomas Bejin over 1 year ago in reply to d_zero

TI__Mastermind 24751 points

Hi,

Typically we see VDD18 and VDDIO come up at same time. let me check back for data on shifting VDDIO and VDD18 timing,

Best,

Thomas

+1 Thomas Bejin over 1 year ago in reply to Thomas Bejin

TI__Mastermind 24751 points

Hi d,

I checked back on the data we have and confirmed that it is okay to bring up either VDD18 or VDDIO first, as long as we have VDD11 / PDB come after VDDIO and VDD18 reach 90%.

Best,

Thomas

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DS90UB9722-Q1: Power Sequence