Original question:
Hello,
No it doesn't automatically toggle high/low on its own. PDB in an input pin, the default state is low, you need to pull it high with an external signal to enable the device. It's an inverted Power-Down input pin, it's typically connected to a processor GPIO with a pulldown.
Datasheet explanation:
When PDB input is brought HIGH, the device is enabled and internal registers and state machines are reset to default values. Asserting PDB signal low will power down the device and consume minimum power. The default function of this pin is PDB = LOW; POWER DOWN with an weak (>100-kΩ) internal pulldown enabled.
PDB should remain low until after power supplies are applied and reach minimum required levels.
PDB = 1, device is enabled (normal operation)
PDB = 0, device is powered down
When the device is in the POWER DOWN state, the LVCMOS outputs are in tri-state, the PLL is shut down, and IDD is minimized.
Regards,
Fadi A.
