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TMDS181: application question

Part Number: TMDS181

Dear team,

We have use TMDS181 in our application, but face to some issue.

Could you share your feedback about below questions?

1. Can we manual control TMDS181 operate in bypass mode (as redriver)? no matter the data rate.

If yes, how to set the mode?

2. Please help to review the schematic and share your feedback if any risk. 

TMS181.pdf

input spec for your reference

Thanks,

Ben

  • 1. Can we manual control TMDS181 operate in bypass mode (as redriver)? no matter the data rate.

    If yes, how to set the mode?

    This can be set at register 0x0A

    This looks like a sink config, so the schematic review ill be done under that assumption.

    Schematic review: 

    1) Need to have either SNK or SRC connected for DDC snooping

    2) Need this implementation for AC coupled output:

    3) Missing 0.2nF capacitor to slow down OE timing:

    4) Im not sure where the following signal are from:

    - SOM_SONY_HPD

    - SOM_I2C_SCK_1

    - SOM_I2C_SDA_1

    5) Clamping voltage is too high on ESD, it should be approx. 4V

    6) From my understanding, HPD is being bypassed and using an external level shifter is this corrct?

    7) consider adding a CMC to improve EMI performance

    Have a look at the following reference schematic found in the datasheet:

  • Here is the schematic checklist I used as reference:

    Checklist: www.ti.com/.../slaa893.pdf

    Datasheet: www.ti.com/.../tmds181.pdf

  • Hi Vishesh,

    Two more questions here,

    1. In Figure1 in previous discussion(external termination). If we set TX_TERM_CTL=L, did we still need to add external pull-up Rterm? 

    2. What is the risk if power on sequence not meet datasheet "td1"(VDD stable before VCC)?  In customer's current design, it's hard to modify power on sequence. 

    How we can know device is working well or not?

    If sequence is invalid and have risk to let device work with something wrong, can we just toggle reset/OE to fix it

    The device have input and output signal, but FPGA cannot recognize the image sensor signal( image sensor -> TMDS181 -> FPGA)

    We are try to know if this is TMDS181 issue or not.

    Regards,

    Ben

  • 1. In Figure1 in previous discussion(external termination). If we set TX_TERM_CTL=L, did we still need to add external pull-up Rterm? 

    Yes, this external pull up is still needed. The TX_TERM_CTL is differentially terminated and does not got to 3.3V. The external pull ups are required for TMDS181 to be recognized as a HDMI source with AC couplings. 

    2. What is the risk if power on sequence not meet datasheet "td1"(VDD stable before VCC)?  In customer's current design, it's hard to modify power on sequence. 

    If the power on sequence is not met, then we cannot guarantee proper device performance. The following parameters must be followed:

    By the looks of it it seems that the there are multiple issue with the system so I cannot say where the issue is originating from. Try changing the issue mentioned in the schematic and layout and see if the device spec can be met. 

  • Im closing this thread due to inactivity