DP83826I: Design review request from EtherCAT requirements

Melbin Manuel

Prodigy 60 points

Part Number: DP83826I

Hello,

We are designing an EtherCAT module with two DP83826I Ethernet Phys.

The interface between the processor and Phys is MII.

Could you please review the design from the EtherCAT requirements and provide comments?

The schematics is attached.

Thanks and Regards,

Melbin

DP83826IRHBT_Schematics.pdf

over 1 year ago

+1 Evan Mayhew over 1 year ago

TI__Mastermind 25048 points

Hi Melbin,

Thanks for your query.

The straps and MAC connections look good to me to default in the correct settings for an EtherCAT application in Enhanced mode for DP83826. I see the Signal Energy Detect strap resistor is DNP'd - do you plan to use Signal Detect?

For general pinout review, please share your inputs on this checklist ("Enhanced Mode Schematic Check" Sheet):

https://www.ti.com/lit/zip/snlr050

I can help share further feedback after reviewing the inputs here.

Thank you,

Evan

+1 Melbin Manuel over 1 year ago in reply to Evan Mayhew

Prodigy 60 points

Hi Evan,

"Enhanced Mode Schematic Check" is filled and attached with this comments.

I look forward to more review comments.

Thanks In advance,

Melbin

DP83826_Schematic_Checklist (public).xlsx

0 Evan Mayhew over 1 year ago in reply to Melbin Manuel

TI__Mastermind 25048 points

Hi Melbin,

Thanks for providing your inputs here.

Please allow me some time to review, I expect to have feedback for you by 5/3.

Best regards,

Evan

0 Evan Mayhew over 1 year ago in reply to Evan Mayhew

TI__Mastermind 25048 points

Hi Melbin,

Please see my feedback below:

LED_1 cannot be connected to the MAC's TX_ER in Enhanced Mode. TX_ER is optional for MII mode, it is okay to leave this pin to just function as an LED / interrupt. Which ESC is being used?
MDIO pull-up resistor should not be DNP'd by default, this is required for register access
Optional capacitors can be added on the MDI termination to improve ESD performance

The rest of the pinout looks good me.

I recommend referring to this layout checklist as you continue with this design:

https://www.ti.com/lit/zip/snlr048

Thank you,

Evan

0 Melbin Manuel over 1 year ago in reply to Evan Mayhew

Prodigy 60 points

Hi Evan,

LED_1 is using for LED purpose only
MDIO pull up is present at the processor side, So depopulated at Phy side
Capacitor on MDI line : Noted

What should be the maximum possible length of the MDI lines on PCB?

We are planning to rout the MDI lines from one board to another board through board to board connector and connect at the RJ45 connector. In this case, where should be the capacitor termination to be placed? Near to the RJ45 connector?

Thanks and regards,

Melbin

0 Evan Mayhew over 1 year ago in reply to Melbin Manuel

TI__Mastermind 25048 points

Hi Melbin,

The MDI trace length should be less than 3 inches from PHY to magnetic. How long is the expected trace length through the board connector?

Termination capacitors should be placed close to the magnetics.

Thank you,

Evan

0 Melbin Manuel over 1 year ago in reply to Evan Mayhew

Prodigy 60 points

Thanks Evan,

The expected length of the MDI signals is 3.5 inches from PHY to magnetics. Will there be any advantage if we rout the signals through inner layers to reduce the risk of exposing to external noise?

4.7pF capacitors will be fine for the MDI termination, right?

Thank you,

Melbin

+1 Evan Mayhew over 1 year ago in reply to Melbin Manuel

TI__Mastermind 25048 points

Hi Melbin,

Routing through inner layer is not recommended, as the vias required for this would affect the impedance and signal quality of the MDI lines. This may be acceptable for 10M applications as a tradeoff for improved noise performance, but this type of layout has not been validated internally.

4.7pF is fine, as shown in the schematic checklist.

Thank you,

Evan

0 Melbin Manuel over 1 year ago in reply to Evan Mayhew

Prodigy 60 points

Thank you Evan.

The comments are noted. Will rout as per the checklist recommendation

Regards,

Melbin

0 Evan Mayhew over 1 year ago in reply to Melbin Manuel

TI__Mastermind 25048 points

Hi Melbin,

Of course, happy to help. I am closing the thread for now, please re-open or create a new thread for further schematic/layout questions.

Thank you,

Evan

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DP83826I: Design review request from EtherCAT requirements