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TS3DV642: connection of the thermal pad with open vias ?

Jochen Lauber
Prodigy 20 points
Part Number: TS3DV642

For PCB cost reasons I would like to avoid plugging of vias below the thermal pad of TS3DV642. 


Is the example of the stencil (on page 33 of datasheet, RUA0042A) meant with open vias  ?

I am afraid open vias will drain away the solder, even if only 69% of the pad is covered with solder.

The thermal pad is the only GND supply pin of the device. No via would then be possible below the thermal pad.
The space between the pads in the corners of the package is not sufficient for routing with the envisaged technology.

Is it possible and sufficient to use the "NC" pins 9 and 30 to connect the thermal pad to GND ? Pins 9 and 30 then would be connected to GND and the routes will be extended into the thermal pad. 

I expect no need for good cooling in my application.


The layer 100µm below the top layer of the PCB will be a GND layer. 
Would the only concern be the HF behaviour (reflections) at GHz regime ? 

Many thanks

  • 0
    TI__Guru*** 145680 points

    Hi:

    TI recommends placing thermal vias in the solder mask defined thermal pad to effectively transfer heat from the top copper layer of the PCB to the inner or bottom copper layers. The thermal vias should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated through hole. Place a ring of exposed copper (0,05 mm wide) around the vias at the bottom copper plane. Do not cover the vias with solder mask which causes excessive voiding. Do not use a thermal relief web or spoke connection which impedes the conduction path into the inner copper layer(s).

    please check this file for TI thermal pad design.

    https://www.ti.com/lit/an/sloa120/sloa120.pdf?ts=1714107815613&ref_url=https%253A%252F%252Fwww.google.com%252F

    Regards

    Brian