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DS125DF1610: High BER, using several retimer in daisychain

TISL
Expert 4640 points
Part Number: DS125DF1610

Dear e2e Support,

My customer uses several End Equipment in daisychain, including our DS125DF1610 (which are therefore themselves in daisychain).

Chaining 3 or 4 End Equipment give a BER which can go below 1e-11, down to 2e-10.

Note that they are not using the DFE in automatic mode (they are fine tuning their settings, depending the temperature, etc...).

The CDR is reset, as it should be, during the initialization.

They are using 10nF AC cap on the TX. Could that be an issue (vs the usual 0.1µF we recommend)?

Should we get AC couplings on the clocks side (from CLK_MON_P/N to REF_CLK_P/N), when we are on this daisy chain configuration?

Are there other precautions we should take care of in daisychain?

Regards,

  • 0
    TI__Mastermind 28050 points

    Hi,

    10nF AC coupling caps have a higher cutoff frequency than 0.1uF coupling caps and this can possibly distort the signal. I recommend replacing these with 0.1uF caps to check if BER performance is improved.

    The customer is likely already aware, but I wanted to highlight that DS125DF1610 has internal AC coupling on the receiver pins. Thus external AC coupling is only needed on the transmitter pins.

    External AC coupling caps are typically used on the REF_CLK pins, but any jitter on the reference clock does not propagate onto the HS signals. As long as the reference clock is meeting datasheet specs, I don't see a need to add AC coupling caps here.

    I have a few questions to better understand the customer's system.

    1. What BER is being targeted? Is it 1E-11?
    2. Can you share a system block diagram so I can better understand which devices are being daisy chained and how the DS125DF1610 fits into this system?
    3. Can you share a register dump of all relevant channels on the DF1610? I'd like to review various statuses/settings to make further recommendations to improve BER performance.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 20 points

    Hello Lucas,

    We tried with 100nF on the transceiver pins and the results are the same.

    We link identical machines with 10Gbase KR on QSFP copper cable.
    Signal is genrerated by a FPGA and after some internal treatment and some internal connectors, the signal is sent to QSFP connector via a DS125DF1610.
    It is receive on another machine via a QSFP connector and a DS125DF1610, sent to a crosspoint and resent to a QSFP connector via another DS125DF1610.
    At the end, the signal is read on the last machine by a FPGA connected to a crosspoint.

    With 2 machines connected, there is no error (4 DS125DF1610 and 3 crosspoints behind the two FPGA).
    With 3 machines, some errors sometimes occur but there are mostly corrected by the FEC (6 DS125DF1610 and 4 crosspoints behind the two FPGA).
    With 4 machines, errors are systematic and are not often corrected (8 DS125DF1610 and 5 crosspoints behind the two FPGA).

    Eye diagrams seen on QSFP cables are good.

    Do you have any idea ?

  • 0 in reply to Matthieu FOURNIER
    TI__Mastermind 28050 points

    Hi Matthieu,

    I have several questions to better understand your system and form debug recommendations.

    1. You mentioned you are using 10GBASE-KR with DS125DF1610. Are auto-negotiation and link training disabled? DS125DF1610 does not support these features.
    2. Can you share a block diagram showing each component included in the signal channel and the channel mapping/crosspoint configuration on each DS125DF1610 unit? I'm having trouble understanding your setup from your description.
    3. What non-default settings are you using on each DS125DF1610?
    4. Can you share full register dumps on all relevant channels of all relevant DS125DF1610 units? I'd like to review various statuses and settings to make further debug recommendations.

    Best,
    Lucas