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DS90UB941AS-Q1: DSI clock detection

Part Number: DS90UB941AS-Q1

Dear expert,

Customer use 0x5A register bit 0,1,3 to validate DSI clock problem during mass production.

But they find when they set to external refclk mode (They have external clock on board), then power down SoC (DSI clk is gone), 0x5A still report 0xC9 which means DSI clock is still valid.

Only when they set to DSI reference clock mode , then power down SoC (DSI clk is gone), 0x5A can report 0x92 which means DSI clock is NOT valid.

Could you comment on this?

Thanks

  • Hey Ryan,

    Are you sure they're checking the proper port? Those bits are port specific they need to make sure to select the correct port. 

    Also, are they running in DSI_CONTINUOUS_CLK mode? If not try to switch and check again. 

    Lastly, can you make sure they're switching to external refclk mode properly via script. 

    Regards,
    Fadi A.

  • Fadi,

    Customer just verified their test again. 

    Yes, they are checking the correct port.

    Yes, they are running in DSI_CONTINUOUS_CLK mode. And they also tried DSI_NON_CONTINUOUS_CLK mode, it is the same phenomenon.

    They configure 0x56 register to 0x1 for external reference clock mode.  0x5A register is always 0xc9 no matter DSI clock is valid or not.

    If they configure 0x56 register to 0x0 for DSI reference clock mode, 0x5A register is 0xc9 when DSI clock is valid and become 0x92 when DSI clock is NOT valid.

    Could you verify in your EVM to confirm?

    Thanks

  • Hi Ryan, 

    This is correct/expected, these frequency detection flags are based upon the selection of "source" CLK. So if programmed into External CLK mode, then it can't be used to detect DSI CLK input. 

    If they are shutting off DSI input/SoC output, then there will likely be several DSI indirect page status/error registers that can be compared and used to detect. Such as the SYNC_STS, or CLK_LANE_ACTIVE in DPHY_STATUS.

    Regards, 

    Logan