DS90UB948-Q1: 948 57:43 provenance

Hello Jeff,

can you provide more details? Duty cycle for what? where is that info written?

Hi,

you can search in datasheet:

7.4.1.1 1-Lane FPD-Link III Input, Single Link OpenLDI Output
In this configuration the PCLK rate embedded within the 1-lane FPD-Link III frame can range from 25 MHz to 96
MHz, resulting in a link rate of 875 Mbps (35 bit × 25 MHz) to 3.36 Gbps (35 bit × 96 MHz). Each LVDS data lane
operates at a speed of 7 bits per LVDS clock cycle; resulting in a serial line rate of 175 Mbps to 672 Mbps. CLK1
operates at the same rate as PCLK with a duty cycle ratio of 57:43.

Hi  Jaradat, 

sorry, form that describe, I still cannot get 57 and 43.

clk1,clk2 follows a 4:3 duty cycle scheme,  how to get 57 and 43?

57 stand for what?

43 stand for what?

best regards,

jeff wang