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DP83867CS: Function failed after reset

Patrick Wohlschiess
Prodigy 10 points
Part Number: DP83867CS

Dear support team,

we determined a functional failure after reset. It is assumed that the RESET_N input of the IC with a newer batch of DP83867CS casing the problem. The reset signal is connected to a capacitor to make it more robust against disturbances, so the signal has a slowly rising edge. With the old revision (see image) the edge has a tau of 1ms and there has never been a problem with the reset, the tau can even be increased to 100ms and there have never be experienced a problem after a reset.

 

We had to reduce the tau to 100us with a newer revision (see image) and in 2% of cases there is still a problem with the reset. It seems that the IC is not initialized correctly after the reset and the chip is not working. With a tau of 100ms the IC does not work after every reset  and cannot be operated.

The question for us now is whether a certain requirement is imposed on the RESET_N signal. Is it possible that a Schmitt trigger must be used? Unfortunately, we could not find a specification for this in the data sheet. 

Thanks,

Patrick

  • 0
    TI__Mastermind 25955 points

    Hi Patrick,

    When you mention 2% of cases is "not working", may I ask what behavior did you observe not working?

    • Is the PHY's register not change to default after the reset?
    • Is the PHY not dropping link after the reset?
    • If possible, May I ask how did you determine the main issue is based on the reset not other parts of the PHY?

    --

    Regards,

    Hillman Lin

  • 0 in reply to Hillman Lin
    Prodigy 10 points

    Hi Hillman,

    thanks for your replay.

    Hillman Lin said:
    Is the PHY's register not change to default after the reset?

    We always use the same default strap configuration. 

    Hillman Lin said:
    Is the PHY not dropping link after the reset?

    The PHY is dropping link after the reset. 

    Hillman Lin said:
    If possible, May I ask how did you determine the main issue is based on the reset not other parts of the PHY?

    Because if we change the capacitor value and thus make the transition edge steeper or less steep, the error occurs more or less frequently, depending on how steep the edge is. Up to a permanent error with a 10uF capacitor, which makes the transition edge relatively flat. This is not the case with the preliminary production batch.  Sorry if this was not quite clear in my description above.

    Regards,

    Patrick

  • 0 in reply to Patrick Wohlschiess
    TI__Mastermind 25955 points

    Hi Patrick,

    Thank you for sharing the description. Here are some information I would like to read for further debug:

    • Could you share the schematic around the PHY?
    • If possible, could you read registers for both working PHY and non working PHY?

    --

    Regards,

    Hillman Lin

  • 0 in reply to Hillman Lin
    Prodigy 10 points

    Hi Hillman,

    sorry for my late response, please find attached the schematic around the PHY. The registers unfortunately I can't read out at the moment.

    Regards,

    Patrick

  • 0 in reply to Patrick Wohlschiess
    TI__Mastermind 25955 points

    Hi Patrick,

    If possible, could you provide the reset connection between PHY and SoC? We want to see if anything we can improve on through schematic connection.

    If possible, could you also share the connection on MDI lines? specially the area around the transformer.

    I will wait for the register information. These information could help me understand the PHY status.

    --

    Thank you,

    Hillman Lin