• State TI Thinks Resolved
  • Locked Locked
  • Replies 11 replies
  • Answers 2 answers
  • Subscribers 33 subscribers
  • Views 336 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB948-Q1: DS90UB948-Q1

xudongwei0398
Prodigy 125 points
Part Number: DS90UB948-Q1

We are using 948 and 949, currently the LOCK signal of 948 is low, may I ask if the CLOCK signal of 948 can also be set high as long as the three pins of MODE_SEL0, MODE_SEL1 and MODE_SEL2 are correctly configured on the hardware and the other registers are not configured?Is there anything on the schematic that needs attention? LOCK is always low, may I ask what causes it?

  • 0
    TI__Guru 66810 points

    Hello, 

    Thanks for your question. By default settings, 948 lock will only go high when there a detected/valid PCLK and video data sent from the SER. Link up will still happen if no video is received when the 949/948 switches to the always-on CLK to achieve link, in this case you will be able to talk to DES but no lock pin will assert. 

    Regards, 

    Logan

  • 0 in reply to Logan Cummins
    Prodigy 125 points

    949/948 How to switch to the alway open CLK to implement the link, in this case the lock pin can not be used as a signal to detect the link is open, then how to detect the link is open?

  • 0 in reply to xudongwei0398
    TI__Guru 66810 points

    Hello, 

    During auto-link during always on clock, the device can be communicated to via I2C channel assuming the proper slave aliasing and passthrough is enabled from SER. Also, 949's 0xC[0] LInk Detect can be used to detect back-channel is present from 948. 

    You can also change the 948 setting  0x34 RX_LOCK_MODE to 1 in order to see lock change without valid PCLK present.

    Regards, 

    Logan

  • 0 in reply to Logan Cummins
    Prodigy 125 points

    948 Set 0x34 RX_LOCK_MODE to 1, the LOCK signal of 948 is still low, what is the possible reason? What about checking those places? Hardware or software?

  • 0 in reply to xudongwei0398
    TI__Guru 66810 points

    Hi, 

    Can you provide full register dump of both SER and DES?

    Was 0x34 modified from the DES local I2C bus?

    There could be HW related reasons why lock isn't established, VDDs out of specification, PDB enable pin low on SER or DES, incorrect pinout of FPD signals, SI issues, component issues on High speed path (capacitor open, etc), etc.

    Can the schematic be provided?

    Regards, 

    Logan

  • 0 in reply to Logan Cummins
    Prodigy 125 points

    948 can now appear pattern, 949 is using the development board, now clok is still low, what is the possible reason? Is there any way to find out?

  • 0 in reply to xudongwei0398
    TI__Guru 66810 points

    Hello,

    Is this using 948 patgen, or is this using video from 949 PG or 949 input? 

    Can you provide register dumps in this condition?

    Regards,

    Logan

  • 0 in reply to Logan Cummins
    Prodigy 125 points

    The internal pattern of 948 can show that 948 and the following links are normal. Currently, the internal pattern of 949 is used to test, and 948 and 949 are linked by coaxial line. Now the lock of 948 is low, what are the directions of investigation?

  • 0 in reply to xudongwei0398
    TI__Guru 66810 points

    Hi,

    xudongwei0398 said:
    what are the directions of investigation?

    I've asked for some information above, can you please provide so we can most accurately and efficiently guide the debug from here? 

    • Local 948 PatGen will not make lock go high if you are not sending the 948 any valid video data. How are you programming the 948 PatGen? Is it from the local 948 bus or from 949?

      So the current configuration after the local 948 patgen test is setting 949 PG? Can you provide the script you are using as well?

      Regards, 

      Logan

  • 0
    Prodigy 125 points

    949 is from the engine factory, 948 is from our product, now 948 can appear internal pattern, after connecting to the 949 terminal of the car, the LOCK is low, we are currently looking for the reason, there is another application that needs to use GPIO1 as the interrupt output pin, and pass through to the serializer. The pin is used as an interrupt signal, and the cockpit controller can initiate fault or event processing after receiving the signal. How do you configure GPIO1 for such applications? Thank you!

  • 0 in reply to xudongwei0398
    TI__Guru 66810 points

    Hello, 

    What is the failure rate, is this just one unit or many systems? This is only one system that has the issue? Does the issue follow the 948 or the SER? 

    There can be many reasons why lock is low in a system. Faulty cable, faulty board component, non-compliant specifications such as return loss/insertion loss/TDR channel specifications, power rails out of DC/AC compliance, and so on. Can you share more of the debug steps done so far so we can provide further guidance on next steps? Are you able to get register dump of 948 in case when no lock is achieved? Can you also provide register dump from good system that is locking?

    Regarding the GPIO interrupt pin, to avoid confusion in this thread on the debugging of lock issue, can you please create a new thread for this topic? 

    Regards, 

    Logan