DP83640: dp83640 internal clock may step abnormally

Hi weiping,

If possible, may I ask what parentage is the board working well?

When you mention "abnormal random value", may I ask what is the abnormal value of the clock signal?

If possible, could you share the scope capture waveform for both working case and non working case?

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Regards,

Hillman Lin 

Hi Hillman，

we design this board for ptp whose phy is dp83640.  

the network works well all the time. But the timestamp in phy is not stable. Sometime the value which is read by PTPClockRead function, change to 0, 533 or 23643 and so on, a random value.  the normal value is like 1715140871(sec) and 238474893(nsec).

At this time the network works well. So the timestamp in the udp packet of ptp is changed to a random value, while the time of slave boards is changed to a wrong time.

HI weiping,

I will discuss with the team and provide you a feedback later this week.

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Regards,

Hillman Lin

Hi Weiping,

I discuss with the team. Here are some of the documents and debug approach:

• We do have some PTP appnote and documents that customer could take a look on:
  • https://www.ti.com/tool/download/DP83640SW-LIB
  • https://www.ti.com/lit/an/snla099d/snla099d.pdf?ts=1715192356062&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDP83640]
• Regarding to the basic functionality, are you able to see any link in your system?
• If possible, could you share the block diagram to understand how did you connect PTP in your system?

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Regards,

Hillman Lin