SLLA284 - Digital Isolator Design Guide - confusion!

andre.robotokogaku

Other Parts Discussed in Thread: ISO7221A

Hello guys,

I'm using the ISO7221A isolators in my design and was reading some application and design notes on the subject.

I'm a bit confused with SLLA284 - Digital Isolator Design Guide, in figure 21. It seems that ground and power planes are short-cut , and I didn't understand what the author wanted to say in the paraghraph soon after the image.

Another doubt I have is that the text says it's good practice to use small vias in high speed PCB designs. On the other hand, I read in Analog Devices' AN-0971 and AN-1109 that we should use large vias to reduce inductance (these ANs are about isolators as well).

Anyone out there with experience with EMC/EMI certification could demystify these doubts?

Thank in advance,

André.

over 13 years ago

0 Roger Liang over 13 years ago

TI__Expert 3510 points

Hi Andre,

Figure 21, the two reference planes should all be ground planes.

While it is true the larger the via the smaller the parasitic inductance, it is also true that the larger the via the larger the parasitic capacitance. Small vias should be used for high-speed signal traces and larger vias should only be used for power paths. To compensate for inductance on small vias, create large "anti-pads" (clearance between via and copper in the gnd and power planes).

Roger Liang

Systems Engineer

Integrated Protection Devices

www.ti.com/esd

0 andre.robotokogaku over 13 years ago in reply to Roger Liang

Intellectual 440 points

Ok!

Thanks, Roger!

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SLLA284 - Digital Isolator Design Guide - confusion!