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DS90UB928Q-Q1: ds90ub928 Output pattern configuration

chen zhang
Prodigy 20 points
Part Number: DS90UB928Q-Q1

The minimum clock frequency of ds90ub928 output pattern is 25M, but the clock range of our screen is 7.32~10.433M. Now we want to complete the time sequence conversion through the distortion correction chip S2D13V40, but the output image is not on the screen, please help to check whether the configuration of ds90ub928 is correct.

Input and output timing of S2D13V40:

 the configuration of ds90ub928

  • 0
    TI__Guru 66840 points

    Hi Chen,

    chen zhang said:
    The minimum clock frequency of ds90ub928 output pattern is 25M, but the clock range of our screen is 7.32~10.433M.

    Can you clarify what PCLK rate you are operating the 928 under? 

    ~8.1MHz is a non-supported use-case, and therefore can't be used for 928. Please increase PCLK over 25MHz for compliant operation of the device. 

    Regards, 

    Logan