DP83822I: timing TX_CLK and MII

Hi Olrik,

I don't see a spec for this in our datasheet. However, I would like to understand the use case of this information in a customer's design. 

Is the PHY in MII mode, not RMII or RGMII?

Is this delay between XI and MII present on all boards produced, regardless of power cycle, reset, etc?

Sincerely,

Gerome

Hi Gerome,

in their application they us the PHY in MII Mode.

The FPGA in the application gives TX_D[3:0] refered to the MII reference clock (=XI). In fact the FPGA Core is a buy in product and don't have access to the timing. Therefore they need to adjust the timing requirements withthe FPGA-logic external of the FPGA core

Current ideaa is ti define TX_DATA refered to the MII reference clock (=XI). Therefore it is required to know the relation of the MII reference clock (=XI) to TX_CLK to keep the specification of the MII-timings of the PHY.

The delay of the ~13ns they measured on several boards and after different power on cycles.

Best wishes

Olrik

HI Olrik,

Checking at the existing data, it appears that this parameter has not been captured and thus cannot be provided. However, I can cross check this against our EVMs to provide additional data. Can you confirm the probe setup point for this so I can recreate?

Sincerely,

Gerome