Team,
There are 3 sources of information for DP83867IR PCB layout:
-Datasheet section 11 https://www.ti.com/lit/pdf/snls484
-Ethernet PHY PCB Design Layout Checklist snla387
-DP83867IRPAP-EVM layout (see EVM UG snlu176 and layout provided in https://e2e.ti.com/support/interface-group/interface---internal/f/interface---internal-forum/1177003/dp83867irpap-evm-layout-file-request/4439891#4439891 )
The keep out region under the magnetics is described slightly differently.
-What document should be followed in this regard for the DP83867IR PCB layout?
Thanks in advance,
Anthony