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DS90UB941AS-Q1: UB941+948, The time sequence resolved is inconsistent with the SOC setting time

Peifeng Shi
Prodigy 20 points
Part Number: DS90UB941AS-Q1

HI ti:

        The timing set by SOC side is as follows(1 clk lane+4 data lane):     

         h_active=1920, hbp=32, hfp=48, hsw=48, v_hactive=720, vbp=4, vfp=4, vsw=8

         pixel clk=91Mhz, dsi rate=600Mbps/lane

         The des is 948, We tried to measure the timing of the 948 output, but but it didn't match what we set in soc.

         Refer to <941 bring up guide.pdf>, which gives the conversion between DSI clock frequency and video PCLK according to the following formula: f_PCLK = (f_DSI*N_Lanes)/12, f_PCLK = (300*4)/12=100Mhz calculated           by this formula is inconsistent with 91M set at the SOC. 

         How does 941 parse the DSI data sent by SOC? How is clock, VFP, VBP, HFP, HBP time sequence reconstructed? 

  • 0
    TI__Mastermind 29715 points

    Hey Shi,

    • How much difference are you seeing in PCLK freq on the 948 side? 
    • How are you measuring the PCLK on 948 side?
    • Do you see any issues in the video on the display?

    For PCLK = 91 Mhz, With 4 lanes your DSI CLK = 273 Mhz and your DSI lane speed is 546 Mbps/lane. 

    You also need to program your TSKIP timing which in this case is 13 so you'd need to program 0x1A to DSI indirect register 0x5. 

    Regards,
    Fadi A.

  • 0 in reply to Fadi Abdulhameed
    Prodigy 20 points

    hi:

    1: PCLK is 98Mhz

    2: we use a lvds->hdmi serdes to check timing, h_active and vactive is right but vfp(8) vbp(10) hfp(30) hbp(48) is error . 

    3:  jittering screen. if we change hbp to 64 , it can be displayed normally

    "For PCLK = 91 Mhz, With 4 lanes your DSI CLK = 273 Mhz and your DSI lane speed is 546 Mbps/lane". This is the theoretical calculation(only pixel), but these don't include frame start and frame end. So we set the DSI lane rate higher.

  • 0 in reply to Peifeng Shi
    Prodigy 20 points

    And we also used 981+948, the same timing config(dsi lane speed 600MBps),iit is ok.

  • 0 in reply to Peifeng Shi
    TI__Mastermind 29715 points

    Hello,

    It's not fully clear what all the analysis that's been done so far but based on below. 

    Peifeng Shi said:
    3:  jittering screen. if we change hbp to 64 , it can be displayed normally

    This seems like a panel sensitivity issue? Just need to adjust the timing to work properly is that correct?

    Regards,
    Fadi A.

  • 0 in reply to Fadi Abdulhameed
    Prodigy 20 points

    Looks like a 941 reconstruction timing error. We also try the same timing config in 981+948 is ok. How does 941 reconstruct the sequence, and how do I confirm that the sequence of 941 reconstruction is correct?

  • 0 in reply to Peifeng Shi
    TI__Mastermind 29715 points

    Hello Shi,

    In order to properly isolate this issue we need to follow the DSI debug guide.

    Can you tell me if you've completed any of the steps in this guide by trying internal timing and internal timing w/external clk and external timing/clk modes? 

    If so can you tell me what are the results. This will help us narrow down whether it's a timing or clk issue, etc. and it will help us identify whether it's coming from the SoC side or whether it's an issue within the FPD-Link datapath, etc.

    2705.DSI Bringup Guide (2).pdf

    Please identify which part of the flow you've tried and where is it passing/failing ? (this diagram can be found on page 8 in the DSI bring-up Guide)

    Regards,
    Fadi A.