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DP83867E: questions

Adam Daluga
Expert 6385 points
Part Number: DP83867E
Other Parts Discussed in Thread: USB-2-MDIO

Hello,

My customer has the below question. Can you help us get to a resolution?

I am looking to utilize the DP83867E with SGMII and would like to use the attached TI user guide schematic reference for the phy on our board.

 snlu325.pdf

Before starting I wanted to be able to confirm if we can purely set the PHY only via strap resistors (no MDIO/MDC control) for 1000Mbps, full-duplex, auto negotiate and any other setting such that the interface would be plug and play?

 

My concern is that currently we have an implementation of DP83867E but with RGMII and MDIO access although it is not plug and play. Meaning that currently we need to send via MDIO to change the PHYCR Force_link_good to 0 so that we can get the port to link up.

 

I wanted to be able to confirm if Force_link_good bit 10 in PHYCR is something that needs to be set for SGMII interface mode as well? And if so, can I set PHYCR bit 10 to 0 via strap resistors such that we can achieve a configured PHY without using MDIO/MDC?

 

Alternatives

  1. Open to hearing any possible alternatives of a similarly spec’d PHY that can be assuredly a plug and play PHY via strap resistors only.
  2. If MDIO is not accessible can JTAG be used to configure the PHY register?

 

Thanks for the help!

Best,

Adam

  • 0
    TI__Mastermind 24998 points

    Hi Adam,

    Adam Daluga said:
    Before starting I wanted to be able to confirm if we can purely set the PHY only via strap resistors (no MDIO/MDC control) for 1000Mbps, full-duplex, auto negotiate and any other setting such that the interface would be plug and play?

    Yes, this can be achieved with just strap configuration. DP83867ERG-S-EVM is a good reference for evaluating this - this EVM uses SGMII and can communicate at 1G full-duplex with strapped config.

    However, in the case of a layout or schematic issue, MDIO/MDC access is strongly recommended for the debug process.

    1. FORCE_LINK_GOOD is not typically required for link up in either SGMII or RGMII, this bypasses the internal PHY blocks that require valid signal quality and amplitude before link-up. For valid schematic and layout, just strap configuration is required with no additional register access.

    2. JTAG cannot be used for register access.

    Thank you,

    Evan

  • 0 in reply to Evan Mayhew
    TI__Expert 6385 points

    Hi Evan,

    Thanks for the help.To confirm my understanding, the PHYCR Force_link_good is not able to be set to 0 via strap resistors only?

     

    As a MDIO/MDC backup for a possible layout or schematic issue,

    1. Short term solution is to use a MSP430F5529LP with USB-2-MDIO to set force_link_good to 0?
    2. Are there any other similar TI PHY options without a force_link_good register?

    Also for the MSP430 option. Once force_link_good is set to 0, can this setting be persistent even if the phy is powered off? Or will this need to be done every time DP83867 is powered on?

    Finally, the customer was wondering if it would be possible for them to order a few of these as evaluation boards? If so they would like to order some

    DP83867 SFP Application Interface Card

    Thanks,

    Adam

  • 0 in reply to Adam Daluga
    TI__Mastermind 24998 points

    Hi Adam,

    Adam Daluga said:
    Meaning that currently we need to send via MDIO to change the PHYCR Force_link_good to 0 so that we can get the port to link up.

    Can you help clarify this? Default value for force_link_good is 0 (normal operation) - are you setting to 1 to force link up?

    Adam Daluga said:
    To confirm my understanding, the PHYCR Force_link_good is not able to be set to 0 via strap resistors only?

    That is correct. Configuring this bit via register access is only recommended for debug, it does not need to be set for functional configuration.

    Adam Daluga said:
    Short term solution is to use a MSP430F5529LP with USB-2-MDIO to set force_link_good to 0?

    I recommend using MSP430LP & USB-2-MDIO to help debug the link issue, there are other status and configuration registers we can check to confirm the correct PHY strap config is set for SGMII, 1G, full-duplex, ... .

    Adam Daluga said:
    Also for the MSP430 option. Once force_link_good is set to 0, can this setting be persistent even if the phy is powered off? Or will this need to be done every time DP83867 is powered on?

    Only strap registers are persistent, all other registers will return to default value on PHY power-up / restart. Force_link_good will always be 0 on power-up, as this is the default setting.

    I don't believe DP83867 SFP Card reference design is available for order, will double-check with team to confirm.

    Thank you,

    Evan