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SN75LVDS83B: timing define

Lillian Liu(SH)
Expert 4090 points
Part Number: SN75LVDS83B

Hi team,

1. If the 10% to 90% rise or fall time is greater than 3 ns, how is the input timing defined?

2. What will be the impact if the 10% to 90% rise or fall time is greater than 3 ns?

Thanks

Lillian

  • 0
    TI__Genius 17890 points

    Hi Lillian,

    The datasheet "7.7 Timing Requirements" section's "Input signal transition time" is maximum 3ns, so the incoming signals should meet that criterion.

    Is there any issue with meeting the rising/ falling edge requirements?

    Best regards,
    Ikram