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TCAN1044AV-Q1: Delay between consecutive frames

Sandeep C
Prodigy 175 points

Part Number: TCAN1044AV-Q1

Tool/software:

Hi, we are using TCAN1044AVDRBRQ1 for our can communication.

MCU: Imxrt1170

Speed:10kbps

Module clock: 24Mhz

To verify the transmission speed of Classical can i did loop back from PCAN viewer to MCU and vice versa.

Working condition

The loop back is working fine, when i keep each frame delay with minimum of 30-40ms its working fine.

Failure condition

when i reduce  delay to less than 30ms seconds, frames are missing, please look in to the shared images of peak can viewer.

So what is the minimum delay required between consecutive frames?

Please verify our schematic once? and how can i overcome this problem?

how can i test individually can transceiver?

Regards,

Sandeep C

  • 0
    TI__Guru 53515 points

    Hi Sandeep,

    Thanks for bringing your question to E2E. 

    The TCAN1044A and similar CAN transceivers are not protocol aware and do not have a minimum delay requirement between frames. Theoretically this device could transmit frames with no delay, such as when a square wave is driven on TXD. The transceiver simply relays the state of TXD onto the CAN pins and the state of the CAN bus onto the RXD pin. 

    The missing frames here are likely the result of one of the CAN controllers in the system having a minimum frame spacing requirement or something similar. Because the timings you describe here are relatively slow for modern controllers, I suspect this may be a configuration issue or a misallocation of data on a higher protocol layer. 

    I've reviewed your schematic see anything wrong here. It does look like your timing configuration may be a bit off - with a clock source of 24MHz and no divisor, the data rate here seems to be > 2Mbps (less than 10 time quanta in the prop seg + sync segs 1 + 2). If this is true, it violates the maximum speed of arbitration for CAN (1Mbps max). How are you deriving the 10kbps data rate here? Is it possible that you need to allocate more time quanta to each bit segment or include a value of the clock divisor?

    Regards, 
    Eric Schott