SN65DP159: Relationship between VDD/VCC startup time and VDD/VCC ramp-up time

Shinichi Inoue

Guru 21646 points

Part Number: SN65DP159

Tool/software:

Dear Specialists,

My customer is considering SN65DP159 and has a question.

I would be grateful if you could advise.

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Regarding SN65DP159,

DatasheetP.20 9.3.2 Operation Timing
There are two regulations listed below regarding VCC/VDD startup.
① VCC/VDD startup timing difference is 200us or less
② VCC/VDD ramp-up time is 100ms or less

listed above, in order to suppress the inrush current, set ② as close to 100ms as possible.
I would like to design it, but then it would be difficult to follow ①.
(Since it is 200us for 100ms, the relative value is very small.)
Could you please let me know if there are any harms caused by not observing ①?

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I appreciate your great help in advance.

Best regards,

Shinichi

over 1 year ago

+1 David (ASIC) Liu over 1 year ago

TI__Guru**** 176991 points

Shinichi-san

There is a note in DP159 datasheet that says "Keeping OE low until VDD and VCC become stable avoids any timing requirements as shown in Figure 22."

So as long as Td2 can be met, then you should be ok.

Thanks

David

0 Shinichi Inoue over 1 year ago in reply to David (ASIC) Liu

Guru 21646 points

Hi David,

Thank you for your reply.

It makes sense.

It seems that using OE will alleviate the customer's concerns.

I'll share with the customer.

I appreciate your great help and cooperation.

Best regards,

Shinichi

+1 David (ASIC) Liu over 1 year ago in reply to Shinichi Inoue

TI__Guru**** 176991 points

Shinichi-san

The OE pin already has an internal 200k pullup, so you would only need an external pulldown capacitor for the passive reset circuit. For more implementation detail, please refer to section 9.3.1.

Thanks

David

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SN65DP159: Relationship between VDD/VCC startup time and VDD/VCC ramp-up time