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TCAN4550EVM: CAN no signal and SPI read 0x81 0x89

Part Number: TCAN4550EVM
Other Parts Discussed in Thread: TCAN4550, TCAN4550-Q1

Tool/software:

I have connected the STM32 and TCAN4550EVM and want to enable CAN FD communication. However, there are no signals being transmitted on the CAN H/L lines. How can this be resolved?

The logic analyzer detected multiple instances of 0x81 and 0x89 on MISO. How can this issue be resolved?

Where can I find information about the error messages returned on MISO?

For HW connection

TCAN4550EVM

  1. TCAN4550EVM is powered by a DC source through J8(->VSUP) on TCAN4550EVM.
  2. VIO SELECT(S1) is chosen to be in 5V output.
  3. CAN H ->CAN H
  4. CAN L ->CAN L
  5. light on : 
    1. nINT
    2. nWKRQ
    3. D2
    4. D3
    5. D4
    6. D5
    7. D6

NUCLEO-WB55 LaunchBoard

  1. spi1_sck   -> SPI CLK
  2. spi1_miso -> SDO
  3. spi1_mosi -> SDI
  4. spi1_nss   -> SPI CS
  5. exti1          ->nINT

For SW configuration

  1. SPI configuration 
    1. The MSP430 uses an 8 MHz clock source, targeting a 2 MHz SPI clock. The STM32 uses a prescaler to set the SPI clock. SPI_BAUDRATEPRESCALER_32 divides the system clock (64 MHz) to 2 MHz.             
    2. Clock Polarity and Phase: The MSP430 is set to EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW and EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT. The corresponding settings for STM32 are SPI_POLARITY_LOW and SPI_PHASE_1EDGE. These settings indicate that the clock is low-level idle, and data is captured on the first edge (rising edge).

    3. Data Bit Order:The MSP430 is set to EUSCI_B_SPI_MSB_FIRST. The STM32 is set to SPI_FIRSTBIT_MSB. Both are MSB first

    4. Data Size: The MSP430 defaults to an 8-bit data size. The STM32 is set to SPI_DATASIZE_8BIT. 

static void MX_SPI1_Init(void)

{

/* SPI1 parameter configuration*/

hspi1.Instance = SPI1;

hspi1.Init.Mode = SPI_MODE_MASTER;

hspi1.Init.Direction = SPI_DIRECTION_2LINES;

hspi1.Init.DataSize = SPI_DATASIZE_8BIT;

hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;

hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;

hspi1.Init.NSS = SPI_NSS_SOFT;

hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;

hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;

hspi1.Init.TIMode = SPI_TIMODE_DISABLE;

hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;

hspi1.Init.CRCPolynomial = 7;

hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;

hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;

}

  1. I modified the TCAN455x Driver Library Demo to make it compatible with STM.

void

AHB_WRITE_BURST_START(uint16_t address, uint8_t words)

{

//STM32

// Set the CS pin low to start the transaction

HAL_GPIO_WritePin(SPI1_NSS_GPIO_Port, SPI1_NSS_Pin, GPIO_PIN_RESET);

// Transmit the AHB write opcode

uint8_t WRITE_OPCODE = AHB_WRITE_OPCODE;

if (HAL_SPI_Transmit(&hspi1, &WRITE_OPCODE, 1, 3) != HAL_OK)

{

/* Transfer error in transmission process */

Error_Handler();

}

while (__HAL_SPI_GET_FLAG(&hspi1, SPI_FLAG_BSY) == SET) {}

// Send the 16-bit address

uint8_t address_high = (address >> 8) & 0xFF; // High byte

uint8_t address_low = address & 0xFF; // Low byte

if (HAL_SPI_Transmit(&hspi1, &address_high, 1, 3) != HAL_OK)

{

/* Transfer error in transmission process */

Error_Handler();

}

while (__HAL_SPI_GET_FLAG(&hspi1, SPI_FLAG_BSY) == SET) {}

if (HAL_SPI_Transmit(&hspi1, &address_low, 1,3) != HAL_OK)

{

/* Transfer error in transmission process */

Error_Handler();

}

while (__HAL_SPI_GET_FLAG(&hspi1, SPI_FLAG_BSY) == SET) {}

// Transmit the number of words to read

if (HAL_SPI_Transmit(&hspi1, &words, 1, 3) != HAL_OK)

{

/* Transfer error in transmission process */

Error_Handler();

}

while (__HAL_SPI_GET_FLAG(&hspi1, SPI_FLAG_BSY) == SET) {}

}

while (__HAL_SPI_GET_FLAG(&hspi1, SPI_FLAG_BSY) == SET) {}

}

void

AHB_WRITE_BURST_WRITE(uint32_t data)

{

// Transmit the data bytes in little-endian order

uint8_t dataBytes[4];

dataBytes[0] = data & 0xFF; // Low byte

dataBytes[1] = (data >> 8) & 0xFF; // Byte 1

dataBytes[2] = (data >> 16) & 0xFF; // Byte 2

dataBytes[3] = (data >> 24) & 0xFF; // High byte

// Transmit each byte of data

if (HAL_SPI_Transmit(&hspi1, &dataBytes[3], sizeof(dataBytes[3]), 3) != HAL_OK)

{

/* Transfer error in transmission process */

Error_Handler();

}

while (__HAL_SPI_GET_FLAG(&hspi1, SPI_FLAG_BSY) == SET) {}

if (HAL_SPI_Transmit(&hspi1, &dataBytes[2], sizeof(dataBytes[2]), 3) != HAL_OK)

{

/* Transfer error in transmission process */

Error_Handler();

}

while (__HAL_SPI_GET_FLAG(&hspi1, SPI_FLAG_BSY) == SET) {}

if (HAL_SPI_Transmit(&hspi1, &dataBytes[1], sizeof(dataBytes[1]), 3) != HAL_OK)

{

/* Transfer error in transmission process */

Error_Handler();

}

while (__HAL_SPI_GET_FLAG(&hspi1, SPI_FLAG_BSY) == SET) {}

if (HAL_SPI_Transmit(&hspi1, &dataBytes[0], sizeof(dataBytes[0]), 3) != HAL_OK)

{

/* Transfer error in transmission process */

Error_Handler();

}

while (__HAL_SPI_GET_FLAG(&hspi1, SPI_FLAG_BSY) == SET) {}

}

void

AHB_WRITE_BURST_END(void)

{

// WAIT_FOR_IDLE;

// Wait for SPI transmit buffer to be empty

while (__HAL_SPI_GET_FLAG(&hspi1, SPI_FLAG_BSY) == SET) {}

// GPIO_setOutputHighOnPin(SPI_CS_GPIO_PORT, SPI_CS_GPIO_PIN);

// Set CS pin high to end the transaction

HAL_GPIO_WritePin(SPI1_NSS_GPIO_Port, SPI1_NSS_Pin, GPIO_PIN_SET);

}

I repeated TCAN4x5x_Device_ClearSPIERR() twice because there was an issue with reading one set of data from the logic analyzer.

The logic analyzer detected multiple instances of 0x81 and 0x89 on MISO. How can this issue be resolved?

Where can I find information about the error messages returned on MISO?

Where can I find information about light on TCAN4550EVM?

  • Hello Hsinyu,

    The Global Error (GLOBALERR) bit is set when one or more other bits are set and will be cleared when there are no other bits set.

    The value of 0x81 means the Global Voltage, Temp or Watchdog (WDTO) bit (VTWD) has been set.  Can you measure and verify all of the voltage rails are at their proper levels? VSUP, VIO, and VCCOUT?  Also, can you measure the voltage on the INH and RST pins?

    The value of 0x89 means that the SPI Error (SPIERR) bit has also been set in addition to the VTWD bit.  Reading register 0x000C will provide more information on why the SPIERR bit is getting set, but it usually comes down to an incorrect number of SPI clocks between the chip select signal transitioning low and then high.

    The SCLK signal appears to have a falling edge after the initial chip select transition low at the beginning of the transaction which may be the problem.  The datasheet shows the SCLK should be low initially so that the first clock edge is a rising edge.

    Here are some additional resources:

    TCAN4550EVM Product folder (Link)

    TCAN4550 Evaluation Module User's Guide (Link)

    TCAN45xx Software User's Guide (Link)

    TCAN4550-Q1 Product folder (Link)

    TCAN4550-Q1 Datasheet (Link)

    Bosch M_CAN User's Manual (Link)

    Regards,

    Jonathan

  • 0x81:

    1. VSUP : 4.6
    2. VIO : 4.6
    3. VCCOUT : 4.6
    4. INH_LU : 4.6
    5. RESET : 0

    0x89:

    1.I use AHB_READ_32(REG_SPI_STATUS); to read hoooc

    Based on the LA display, does 0A000000 indicate issues with bits 25 and 27?

    27: Entry written to the internal error log

    25: Read FIFO empty for the first read data word to return


    2. I found an issue with the SPI clock: each group of clock pulses normally has an interval of 250ns, but there randomly appears a pulse with an interval of 333ns.

  • Hi Hsinyu,

    I think your primary problem is that the VSUP Supply Voltage is too low.  This voltage must be greater than 5.5V and you are only providing it 4.6V which will cause the device to be in an under-voltage state.

    Please provide a larger supply voltage and see if the SPI communication issues are resolved. 

    The SPI signals are all edge based and a slightly larger clock pulse width should not cause a problem as long as the sample point of the data bit is not affected to a point where the setup/hold times are violated such that a bit error would occur.

    Regards,

    Jonathan

  • Hi Jonathan,

    Thanks to you advice.

    I used  12v power supply now.

    1. VSUP : 11.5
    2. VIO : 4.96
    3. VCCOUT : 4.96
    4. INH_LU : 4.96
    5. RESET : 0

    SPI read  0xC8 0xC0.

    Have I looked up the correct information based on the SPI messages?

    However, my CAN bus is still not able to transmit.

    Also, after I switched to 12V, I noticed that the INT pin and MISO were still sending messages after the previous communication ended.

    Could it be that my INT pin is not configured correctly, causing me to miss messages?

  • Hi Hsinyu,

    The SPI Error (SPIERR) bit appears to be getting set and is indicated as bit 3 in the 0xC8 Global Status Byte that is returned on the MISO line on every SPI transaction.  This means there is something incorrect with the SPI.  If a SPI error occurs on a Write, the TCAN4550 will discard that transaction and the register will not be updated.  If a SPI error occurs on a Read, then the data returned may be incorrect. 

    Your Logic Analyzer plots have too many bits for me to see what may be incorrect with them.  Is it possible to just capture single read and write transactions with enough resolution to see if the placement of the clock edge relative to the data?  Ideally can you capture a single SPI transaction that shows the chip select going low and then high again that fills the entire window?

    Regards,

    Jonathan

  • Hi Jonathan,

    I use AHB_READ_32(REG_SPI_STATUS); to read hoooc

    Based on the LA display, I read 0x88 0x00 0x00 0x00 0x00 0x02 0x00 0x0A 0x00 0x00 0x00

  • Hi Hsinyu,

    The chip select signal is remaining low after the SPI transaction should have completed.  The TCAN4550 works on a 32-bit "word" or 4-byte system and there must be an exact number of clock cycles to prevent a SPI error.

    If the clock cycles seen is not a multiple of 32, then a SPI error will occur.

    Also, if the number of clock cycles does not match the number indicated by the Length field, then an SPI error will occur.  A Single register read or write transaction requires 64-bits.  The first 32-bits is from the Header word that contains the R/W operation code byte, the Address bytes, and the Length field.  The second 32-bit word is the Data field.  Together this means there should be 64 SPI clock cycles for a SPI Read or Write with Length field = 1.

    If multiple consecutive registers are to be read or written, then there will be an additional 32 clock cycles needed for each additional word indicated by the length field.  For example, there are 96 clock cycles needed when Lengh = 2.

    SPI Clock Cycles = 32 + (Length * 32)

    You will need to adjust the driver so that the chip select transitions high after the proper number of clock cycles.

    Regards,

    Jonathan

  • Hi Jonathan,

    Thank you for your help.

    The issue was indeed because the number of clock cycles did not match the number indicated by the Length field. The reason was that I separated the read register into individual read and write operations, which resulted in three extra clock cycles.

    Now the CAN communication is working properly.

  • Hi Hsinyu,

    Great, I'm glad we could resolve the issue.  I you have any additional questions please let us know.

    Regards,

    Jonathan