DS90UB941AS-Q1: Resolving the DSI signal correlation problem using TI941

Dear Ben：

    I used the internal clk and timing output pattern of the 948. The LVDS2HDMI adapter chip can be parsed normally, and the external clk (from the 941) and the internal timing of the 948 can also be parsed normally. However, with external clk (from 941) and external timing (from 941), it doesn't parse properly. Using 941 internal clk and timing out pattern, normal parsing; Using 941 external clk (clk of soc dsi) and internal timing out pattern can also resolve properly, then using external clk (from soc dsi) and external timing (from soc dsi), it cannot resolve properly. Is there a problem with 941 parsing dsi signal? The specific configuration of my TI941+948 is as follows:

Notes: The first column represents reg, the second column represents the value written to reg, and AS means toggles i2c addr, 0xc is the actual address of TI941, 0x1A is the slave alias ID(actual address is 0x2c) from TI948 address hanging on TI941 port0, 0x1B is the slave alias ID(actual address is 0x2c) from TI948 addr hanging on TI941 port1.

AS, 0x0C
0x01, 0x0F
0x63, 0x09
0x5B, 0x07
0x1E, 0x04
AS, 0x0C
0x03, 0x9A
0x07, 0x58
0x08, 0x34
0x17, 0x9E
0x56, 0x00
0x4F, 0x8C
0x0D, 0x03
0x34, 0xC8
AS, 0x1A
0x05, 0x9E
0x1D, 0x05
0x1E, 0x90
0x49, 0x62
AS, 0x0D
0x03, 0x9A
0x07, 0x58
0x08, 0x36
0x17, 0x9E
0x56, 0x00
0x4F, 0x8C
0x0D, 0x03
0x34, 0xC8
AS, 0x1B
0x05, 0x9E
0x1D, 0x09
0x1E, 0x90
0x49, 0x62
AS, 0x0C
0x40, 0x04
0x41, 0x05
0x42, 0x1E
0x41, 0x20
0x42, 0x7F
0x41, 0x21
0x42, 0x01
0x01, 0x00

Hi Loki,

What mode is the SoC in (burst mode, non-burst mode with sync pulses, or non-burst mode with sync events)? What is the DSI rate and what is the PCLK?

Please see the below document for info on DSI bring-up with this device.

DSI Bring-up Guide snla356.pdf

Regards,

Ben

Dear ben：

    non-burst mode with sync pulses，DSI rate is 630M/lane， PCLK is 52MHz. I have read this document, and I have also caught the DSI data packet output by the soc side, and found that the timing in the data packet is also correct. No other problems were found, so I would like to ask you to help take a look.

Hi Loki,

This DSI rate does not match the PCLK. Per DSI spec, in non-burst modes, the DSI rate needs to match the PCLK based on the below equation:

fPCLK = (fDSI*NLanes)/12

For the DSI rate of 630Mbps/lane with 4 lanes, the PCLK would be the following:

fPCLK = (315MHz*4Lanes)/12 = 105MHz

This does however appear correct if the DSI source is outputting a superframe of two 52MHz images. Are you using a superframe? And if so, you need to crop this image for each individual image using the cropping registers in the 941AS.

Can you check the DSI indirect registers as well to see if there is any error status?

Regards,

Ben

Dear Ben,

    We use Splitting With VC-IDs, not superframe.Block diagram is as follows:

    It appears that the 941 parsed dsi timing is incorrect.Is there any solution or suggestion?

Hi Loki,

Do you mean you are using interleaved VCs? What is the DSI source you are using?

Regards,

Ben

Dear Ben,

    The DSI signal output by our SOC will pack two VC data, one packet of VC0 and one packet of VC1 data are output alternately (one packet in a row), and the arrangement is the same as that in TI941 spec：

Hi Loki,

Can you provide a dump of the indirect DSI registers?

Regards,

Ben

Dear Ben,

TI941 indirect registers dump:

TI941 PORT0 indirect reg
0x0: 0x0
0x1: 0x0
0x2: 0x0
0x3: 0x1d
0x4: 0x14
0x5: 0x1e
0x6: 0x0
0x7: 0x0
0x8: 0x0
0x9: 0x0
0xa: 0x0
0xb: 0x0
0xc: 0x0
0xd: 0x0
0xe: 0x0
0xf: 0x1f
0x10: 0x0
0x11: 0x0
0x12: 0x0
0x13: 0x0
0x14: 0x0
0x15: 0x0
0x16: 0x0
0x17: 0x0
0x18: 0x0
0x19: 0x0
0x1a: 0x0
0x1b: 0x0
0x1c: 0x0
0x1d: 0x0
0x1e: 0x0
0x1f: 0x0
0x20: 0x5f
0x21: 0x1
0x22: 0xff
0x23: 0x7f
0x24: 0x0
0x25: 0x0
0x26: 0x0
0x27: 0x0
0x28: 0x0
0x29: 0x0
0x2a: 0x3e
0x2b: 0x0
0x2c: 0x0
0x2d: 0x0
0x2e: 0x0
0x2f: 0x0
0x30: 0x0
0x31: 0x20
0x32: 0x0
0x33: 0x4
0x34: 0x0
0x35: 0x20
0x36: 0x0
0x37: 0x0
0x38: 0x0
0x39: 0x0
0x3a: 0x2
0x3b: 0x3
0x3c: 0x0
0x3d: 0x0
0x3e: 0x0
0x3f: 0x0
0x40: 0x0
0x41: 0x0
0x42: 0x0
0x43: 0x0
0x44: 0x0
0x45: 0x0
0x46: 0x0
0x47: 0x0
0x48: 0x0
0x49: 0x0
0x4a: 0x0
0x4b: 0x0
0x4c: 0x0
0x4d: 0x0
0x4e: 0x0
0x4f: 0x0
0x50: 0x0
0x51: 0x0
0x52: 0x0
0x53: 0x0
0x54: 0x0
0x55: 0x0
0x56: 0x0
0x57: 0x0
0x58: 0x0
0x59: 0x0
0x5a: 0x0
0x5b: 0x0
0x5c: 0x0
0x5d: 0x0
0x5e: 0x0
0x5f: 0x0
0x60: 0x0
0x61: 0x0
0x62: 0x0
0x63: 0x0
0x64: 0x0
0x65: 0x0
0x66: 0x0
0x67: 0x0
0x68: 0x0
0x69: 0x0
0x6a: 0x0
0x6b: 0x0
0x6c: 0x0
0x6d: 0x0
0x6e: 0x0
0x6f: 0x0
0x70: 0x0
0x71: 0x0
0x72: 0x0
0x73: 0x0
0x74: 0x0
0x75: 0x0
0x76: 0x0
0x77: 0x0
0x78: 0x0
0x79: 0x0
0x7a: 0x0
0x7b: 0x0
0x7c: 0x0
0x7d: 0x0
0x7e: 0x0
0x7f: 0x0
0x80: 0x0
0x81: 0x0
0x82: 0x0
0x83: 0x0
0x84: 0x0
0x85: 0x0
0x86: 0x0
0x87: 0x0
0x88: 0x0
0x89: 0x0
0x8a: 0x0
0x8b: 0x0
0x8c: 0x0
0x8d: 0x0
0x8e: 0x0
0x8f: 0x0
0x90: 0x0
0x91: 0x0
0x92: 0x0
0x93: 0x0
0x94: 0x0
0x95: 0x0
0x96: 0x0
0x97: 0x0
0x98: 0x0
0x99: 0x0
0x9a: 0x0
0x9b: 0x0
0x9c: 0x0
0x9d: 0x0
0x9e: 0x0
0x9f: 0x0
0xa0: 0x0
0xa1: 0x0
0xa2: 0x0
0xa3: 0x0
0xa4: 0x0
0xa5: 0x0
0xa6: 0x0
0xa7: 0x0
0xa8: 0x0
0xa9: 0x0
0xaa: 0x0
0xab: 0x0
0xac: 0x0
0xad: 0x0
0xae: 0x0
0xaf: 0x0
0xb0: 0x0
0xb1: 0x0
0xb2: 0x0
0xb3: 0x0
0xb4: 0x0
0xb5: 0x0
0xb6: 0x0
0xb7: 0x0
0xb8: 0x0
0xb9: 0x0
0xba: 0x0
0xbb: 0x0
0xbc: 0x0
0xbd: 0x0
0xbe: 0x0
0xbf: 0x0
0xc0: 0x0
0xc1: 0x0
0xc2: 0x0
0xc3: 0x0
0xc4: 0x0
0xc5: 0x0
0xc6: 0x0
0xc7: 0x0
0xc8: 0x0
0xc9: 0x0
0xca: 0x0
0xcb: 0x0
0xcc: 0x0
0xcd: 0x0
0xce: 0x0
0xcf: 0x0
0xd0: 0x0
0xd1: 0x0
0xd2: 0x0
0xd3: 0x0
0xd4: 0x0
0xd5: 0x0
0xd6: 0x0
0xd7: 0x0
0xd8: 0x0
0xd9: 0x0
0xda: 0x0
0xdb: 0x0
0xdc: 0x0
0xdd: 0x0
0xde: 0x0
0xdf: 0x0
0xe0: 0x0
0xe1: 0x0
0xe2: 0x0
0xe3: 0x0
0xe4: 0x0
0xe5: 0x0
0xe6: 0x0
0xe7: 0x0
0xe8: 0x0
0xe9: 0x0
0xea: 0x0
0xeb: 0x0
0xec: 0x0
0xed: 0x0
0xee: 0x0
0xef: 0x0
0xf0: 0x0
0xf1: 0x0
0xf2: 0x0
0xf3: 0x0
0xf4: 0x0
0xf5: 0x0
0xf6: 0x0
0xf7: 0x0
0xf8: 0x0
0xf9: 0x0
0xfa: 0x0
0xfb: 0x0
0xfc: 0x0
0xfd: 0x0
0xfe: 0x0
TI941 PORT1 indirect reg
0x0: 0x0
0x1: 0x0
0x2: 0x0
0x3: 0x1d
0x4: 0x14
0x5: 0x1e
0x6: 0x0
0x7: 0x0
0x8: 0x0
0x9: 0x0
0xa: 0x0
0xb: 0x0
0xc: 0x0
0xd: 0x0
0xe: 0x0
0xf: 0x10
0x10: 0x0
0x11: 0x0
0x12: 0x0
0x13: 0x0
0x14: 0x0
0x15: 0x0
0x16: 0x0
0x17: 0x0
0x18: 0x0
0x19: 0x0
0x1a: 0x0
0x1b: 0x0
0x1c: 0x0
0x1d: 0x0
0x1e: 0x0
0x1f: 0x0
0x20: 0x5f
0x21: 0x1
0x22: 0xff
0x23: 0x7f
0x24: 0x0
0x25: 0x0
0x26: 0x0
0x27: 0x0
0x28: 0x0
0x29: 0x0
0x2a: 0x0
0x2b: 0x0
0x2c: 0x0
0x2d: 0x0
0x2e: 0x0
0x2f: 0x0
0x30: 0x0
0x31: 0x20
0x32: 0x0
0x33: 0x4
0x34: 0x0
0x35: 0x20
0x36: 0x0
0x37: 0x0
0x38: 0x0
0x39: 0x0
0x3a: 0x2
0x3b: 0x3
0x3c: 0x0
0x3d: 0x0
0x3e: 0x0
0x3f: 0x0
0x40: 0x0
0x41: 0x0
0x42: 0x0
0x43: 0x0
0x44: 0x0
0x45: 0x0
0x46: 0x0
0x47: 0x0
0x48: 0x0
0x49: 0x0
0x4a: 0x0
0x4b: 0x0
0x4c: 0x0
0x4d: 0x0
0x4e: 0x0
0x4f: 0x0
0x50: 0x0
0x51: 0x0
0x52: 0x0
0x53: 0x0
0x54: 0x0
0x55: 0x0
0x56: 0x0
0x57: 0x0
0x58: 0x0
0x59: 0x0
0x5a: 0x0
0x5b: 0x0
0x5c: 0x0
0x5d: 0x0
0x5e: 0x0
0x5f: 0x0
0x60: 0x0
0x61: 0x0
0x62: 0x0
0x63: 0x0
0x64: 0x0
0x65: 0x0
0x66: 0x0
0x67: 0x0
0x68: 0x0
0x69: 0x0
0x6a: 0x0
0x6b: 0x0
0x6c: 0x0
0x6d: 0x0
0x6e: 0x0
0x6f: 0x0
0x70: 0x0
0x71: 0x0
0x72: 0x0
0x73: 0x0
0x74: 0x0
0x75: 0x0
0x76: 0x0
0x77: 0x0
0x78: 0x0
0x79: 0x0
0x7a: 0x0
0x7b: 0x0
0x7c: 0x0
0x7d: 0x0
0x7e: 0x0
0x7f: 0x0
0x80: 0x0
0x81: 0x0
0x82: 0x0
0x83: 0x0
0x84: 0x0
0x85: 0x0
0x86: 0x0
0x87: 0x0
0x88: 0x0
0x89: 0x0
0x8a: 0x0
0x8b: 0x0
0x8c: 0x0
0x8d: 0x0
0x8e: 0x0
0x8f: 0x0
0x90: 0x0
0x91: 0x0
0x92: 0x0
0x93: 0x0
0x94: 0x0
0x95: 0x0
0x96: 0x0
0x97: 0x0
0x98: 0x0
0x99: 0x0
0x9a: 0x0
0x9b: 0x0
0x9c: 0x0
0x9d: 0x0
0x9e: 0x0
0x9f: 0x0
0xa0: 0x0
0xa1: 0x0
0xa2: 0x0
0xa3: 0x0
0xa4: 0x0
0xa5: 0x0
0xa6: 0x0
0xa7: 0x0
0xa8: 0x0
0xa9: 0x0
0xaa: 0x0
0xab: 0x0
0xac: 0x0
0xad: 0x0
0xae: 0x0
0xaf: 0x0
0xb0: 0x0
0xb1: 0x0
0xb2: 0x0
0xb3: 0x0
0xb4: 0x0
0xb5: 0x0
0xb6: 0x0
0xb7: 0x0
0xb8: 0x0
0xb9: 0x0
0xba: 0x0
0xbb: 0x0
0xbc: 0x0
0xbd: 0x0
0xbe: 0x0
0xbf: 0x0
0xc0: 0x0
0xc1: 0x0
0xc2: 0x0
0xc3: 0x0
0xc4: 0x0
0xc5: 0x0
0xc6: 0x0
0xc7: 0x0
0xc8: 0x0
0xc9: 0x0
0xca: 0x0
0xcb: 0x0
0xcc: 0x0
0xcd: 0x0
0xce: 0x0
0xcf: 0x0
0xd0: 0x0
0xd1: 0x0
0xd2: 0x0
0xd3: 0x0
0xd4: 0x0
0xd5: 0x0
0xd6: 0x0
0xd7: 0x0
0xd8: 0x0
0xd9: 0x0
0xda: 0x0
0xdb: 0x0
0xdc: 0x0
0xdd: 0x0
0xde: 0x0
0xdf: 0x0
0xe0: 0x0
0xe1: 0x0
0xe2: 0x0
0xe3: 0x0
0xe4: 0x0
0xe5: 0x0
0xe6: 0x0
0xe7: 0x0
0xe8: 0x0
0xe9: 0x0
0xea: 0x0
0xeb: 0x0
0xec: 0x0
0xed: 0x0
0xee: 0x0
0xef: 0x0
0xf0: 0x0
0xf1: 0x0
0xf2: 0x0
0xf3: 0x0
0xf4: 0x0
0xf5: 0x0
0xf6: 0x0
0xf7: 0x0
0xf8: 0x0
0xf9: 0x0
0xfa: 0x0
0xfb: 0x0
0xfc: 0x0
0xfd: 0x0
0xfe: 0x0

Dear Ben,

    The first column represents reg and the second column represents the read out data.

Hi Loki,

Can you confirm the source is sending periodic LP-11 transitions?

Can you also confirm that the DSI clock is continuous?

Regards,

Ben

Dear Ben,

    DSI clock is continuous, The data lane sends periodic LP-11 transitions.

Hi Loki,

Do you have access to a DSI protocol analyzer? It may be helpful for us to look at the packet structure and order.

Regards,

Ben

Dear Ben,

   Take a look at this.

Dear Ben,

   The DSI rate set for this captured data is 650MHz.

Hi Loki,

Do you mean the rate is 650Mbps or the frequency is 650MHz? The frequency is related to the PCLK, and the rate is usually half of the frequency. Regardless, this is a higher rate than you previously mentioned (630Mbps). The TSKIP value is based on the DSI frequency, so this change would invalidate the programmed TSKIP value. This could very well be the problem. The TSKIP value needs to be programmed correctly.

Regards,

Ben

Dear Ben,

   DSI rate is 650Mbps, The TSKIP I have changed to 0x10 (Fdsi * 65 -5 = 0x10).

Hi Loki,

Please note that the TSKIP value should be written in bits[6:1] so the written value should be 0x20 for fDSI=325MHz. 

Did this make any difference?

Regards,

Ben

Dear Ben,

    I tried to change this to 0x20 and it didn't improve.

Hi Loki,

If the DSI rate is 650MHz now, I would expect the video timing to change as well unless you are in burst mode. Can you confirm this? I am not sure why the timing you are reporting is different than before but it could be why you are seeing an issue.

Regards,

Ben

Dear Ben,

    When the dsi rate is set to 630Mbps, the oscilloscope analyzes many error data packets. We suspect that the low rate is caused, because 630M is almost completely calculated according to the screen parameter data, and there are some ECC, CRC and other data in the DSI transmission process. Therefore, we increased the rate to 650M, so that the data parsed by the oscilloscope would have no wrong data. When it is set to 650M, I also use sync pluse mode on my side.

Hi Loki,

Since you are using non-burst mode, then changing the DSI rate is also changing your pclk. With the new DSI rate, your total pclk should be 108.33MHz.

Regards,

Ben

Dear Ben,

    For example, for a 1024x600 screen with 320 Hblank and 35 Vblank, the required pclk is about 51.2MHz. For the dsi side, if the dsi rate is set to 307.2Mbps, this rate transmission is theoretically not enough, because the dsi will also have DI, ECC, checksum and other data, and generally the dsi rate is larger than the pclk required by the screen. In this case, the pclk of TI941 will be larger after parsing dsi rate. How do you deal with this? Or should they all have problems?

Dear Ben,

    So for my case, if I set the total pclk to 108.33MHz, the DSI rate would have to be higher (greater than 650M).

Hi Loki,

loki zhang said:

In this case, the pclk of TI941 will be larger after parsing dsi rate. How do you deal with this? Or should they all have problems?

Per the DSI spec, in non-burst mode, the DSI clk is directly related to PCLK by the equation below:

Only in burst mode is the pclk and DSI clk separated. In non-burst mode, increasing the DSI clock will also increase the PCLK and could cause timing issues.

Regards,

Ben