• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 299 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867IR: DP83867IRPAPR : About PHY Placement

Si Yoon Kim
Intellectual 710 points
Part Number: DP83867IR

Tool/software:

Dear Team

I would like to design a circuit using the "DP83867IRPAPR" PHY.

[RJ45 - Lan Trans - PHY - SOC ]

The BD is designed separately from [RJ45-LAN TRANS] and [SOC], and the two BDs are connected with a cable.

Total Ethernet Legnth is the same, but MDI / MII Length varies depending on PHY placement

If the PHY is placed on the [RJ45-LAN TRANS] BD, the MDI analog signal will be shortened, which seems to be advantageous for EMC.

However, there are many PHY signals that must be connected to the SOC with cables, and the connector area is likely to be weak to EMC.

On the other hand, if the PHY is placed in the [SOC] BD, the MDI analog signal becomes longer, which is likely to be disadvantageous to EMC.

However, since the only signal connected to the Lan Transformer is the MDI Line, signal loss at the connector is likely to be minimal.

Through www.ti.com/.../snla387.pdf, MDI Max Trace was confirmed to be 2000 mils and MII Max Trace was confirmed to be 6000 mils.

There will be no problem with communication, but it seems important to keep the MDI signal short in terms of EMC, but I am not sure.

Please let me know your thoughts. 

Thank you.

  • 0
    TI__Mastermind 19621 points

    Hi Si Yoon Kim,

    This is an excellent question. I understand the predicament in the layout, it would be better to keep the MDI traces shorter. That being said, the MII signals still need to be l<6000 mils.

    Regards,

    Alvaro

  • 0 in reply to Alvaro (Al-vuh-roe) Reyes
    Intellectual 710 points

    Dear Team

    I am very grateful for your answer.

    Since it is GIGABIT Ethernet communication("DP83867IRPAPR"), I am concerned about EMC (Conducted Immunity , ESD..).

    Therefore, I want to design in a way that is more advantageous to EMC (Conducted Immunity , ESD..).

    -Case 1.-
    [PCB1]                                                    [PCB2]
    [RJ45-LAN TRANS] + [Connector] + [PHY-SOC]

    It is advantageous for maintaining the integrity of MII signals and digital signals, and since the PHY and SOC are located on the same PCB, interference from other digital signals is likely to be minimized.
    However, MDI signal transmission through the connector is likely to be vulnerable to signal attenuation, noise, and reflection.
    Additionally, since RJ45 and LAN TRANS are on a different PCB from the PHY, it seems difficult to place the ESD protection circuit efficiently.

    -Case 2.-
    [PCB1]                                                            [PCB2]
    [RJ45-LAN TRANS-PHY] + [Connector] + [SOC]

    Since RJ45 and LAN TRANS have the same PHY on the PCB, the MDI path is short, which seems to be advantageous for signal attenuation, noise, and reflection.
    It also seems easy to deploy the ESD protection circuit efficiently.
    However, because MII signals and digital signals are transmitted through connectors, there is a possibility that signal integrity may deteriorate and some transmission delay may occur.

    From an EMC perspective, we are considering which of the two cases is more advantageous.

    It would be of great help if you shared your opinion.

    Thank you.

  • +1 in reply to Si Yoon Kim
    TI__Mastermind 19621 points

    Hi Si Yoon Kim,

    I have personally used several daughter cards with our PHY, transformer, and RJ45 onboard with only the MII signals going through the connector, function without error. Case 2 would be the better option.

    Regards,

    Alvaro