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DS100KR401: DS100KR401-BER

Nirmal Bommu
Prodigy 60 points
Part Number: DS100KR401

Tool/software:

I am using this re-driver between a FPGA & SFP-ER  as per below mentioned block diagram, with maximum of 10Gbps data rate system. BER for some lane is so much high using IBERT (xilinx tool). By generating the eye diagram in the IBERT tool, BER 0E0 & error causing channels looks the same. Is there any option to monitor signal quality parameters.

And in that re-drive 2 types of physical mode given, Pin No 21. 10G-BASE-KR & 10G-Mode, clarity required for 10G-Mode.

  • 0
    TI__Guru* 93670 points

    Hi Nirmal,

    You can put scope at the output of the device to monitor signal through the device and transmission media.

    Pin 21 defines whether the device will operate in linear mode - act like analog buffer - or limiting mode -output is either one or zero. Would it be possible to enable limiting mode(pin 21 1K to GND) and check bit error at 1G and 10G? You may need to change EQ pins - starting from minimum - to optimize the output eye diagram.

    Regards, Nasser