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SN65HVD24：匹配电阻和总线上拉/下拉电阻是否冲突的问题

技术 科力
Prodigy 10 points
Part Number: SN65HVD24

Tool/software:

1。应用架构：受限于产品架构，从机1没有完全按照菊花链架构设计，属于设计缺陷；各节点之间通过20cm的排线连接（非屏蔽双绞线）。

2。节点原理：

3.测试主机带单节点时的AB波形：

4.问题：（1）这颗芯片这样使用（架构、连接方式、速率）是否合适，虽然可以正常通信，但总感觉和芯片手册推荐的电路差距有些大；（2）波形并不是标准方波，且存在变形，如何进行进一步优化；（3）收发使能信号切换时，对波形有一定的影响，虽然没影响通信，但如何降低影响（4）在上述情况下为何加了匹配电阻（去掉上下拉电阻后）会报错，匹配电阻到底什么时候加

  • 0
    Guru 275330 points

    1. The driver is guaranteed to output at least ±1.8 V when connected to a standard 54 Ω load. Increasing the load current will decrease the bus voltage (see figure 8-4; you have to extrapolate for larger currents). RS-485 receivers actually can switch with ±0.2 V, so it might indeed be possible that a bus with 15 termination resistor still works. However, this is not guaranteed at all, and even if it happens to works in your test, you have lost most of the noise margin.

    2. For differential signals, only the difference matters. Please tell your oscilloscope to compute A − B.

    3. You can try to remove common-mode noise with a common-mode choke (at each transceiver).

    4. An RS-485 bus should have exactly two termination resistors, at the two ends of the bus. In your application, you should have termination only at nodes 1 and 14.