• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 33 subscribers
  • Views 573 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867E: CLK_OUT reset behavior; chaining clocks

Marek Kvas
Prodigy 51 points
Part Number: DP83867E


Tool/software:

Dear TI team,

I have some related questions about DP83867E's CLK_OUT signal.

1) DS states:

From that I understand that I can route CLK_OUT output of one PHY to XI of the other one. How many PHYs can be chained in this way?

2) How do CLK_OUT output behave during reset and power down?

3) If I reset e.g. the first PHY in the chain, does it stop its CLK_OUT clock, so function of other PHY is disrupted and all PHYs need to be reset too?

4) Can I safely release reset of all the PHYs in chain at once?

5) DS also states that PHY doesn't need explicit reset after power-on. Is it still true for chained PHYs?

6) All diagrams in DS show clock running before power-up. This cannot be done in chain of PHYs. I haven't found such condition in text of DS and it seems to me that in case of using crystal it is not fulfilled either. Is there any real requirement on clock being stable before power-up?

Thanks for information

Best regards

Marek

  • 0
    TI__Mastermind 26035 points

    Hi Team,

    1) Normally, CLK_OUT are used mainly for debugging or testing purpose. If customer want to perform this test. Please do make sure CLK_OUT satisfy the clock constraint in the datasheet. The clock will worsen if multiple clock daisy chain involve

    2)There won't be any LK_OUT in reset and power down mode

    3) Yes, if you clock got disturb. It might require reset or even power cycle to recover the clock

    4) We don't recommend this approach because clock need to be stable before the power up for all the PHY. there might be delay from one PHY's clk to clkout to another PHY's clk

    5) Refer to point 4 above.

    --

    Regards,

    Hillman Lin

  • 0 in reply to Hillman Lin
    Prodigy 51 points

    Thank you for the answer. I will avoid chaining of PHYs.

    Let me just say that I find the documentation confusing and misleading. The datasheet says exactly this: "The default output clock is suitable for use as the reference clock of another DP83867 device". Is it just a bug in documentation?

    Thanks

    Marek

  • 0 in reply to Marek Kvas
    TI__Mastermind 26035 points

    Hi Marek,

    I check it with the team. CLK_OUT could be use as reference clock for another DP83867PHY, but we don't recommend to have multiple daisy chain.

    If you are using other PHY as link partner, please check the datasheet spec on the input clock.

    --

    Regards,

    Hillman Lin

  • 0 in reply to Hillman Lin
    Prodigy 51 points

    Thanks for the update.

    Did you also discuss other aspects of using CLK_OUT as reference clock source?

    Are you sure about reset interrupting CLK_OUT? This spoils the fun a bit.

    Are you sure about requirement of XI running before power up? This spoils the fun a lot. I would have to have independent power supplies for each PHY to ensure this. I also found this thread:https://e2e.ti.com/support/interface-group/interface/f/interface-forum/616699/dp83867e-xi-clock-timing-when-powering-up

    where your colleague agrees it is possible to power up PHY without valid clock. I can easily ensure RESET after power up or during power up, but ensuring XI valid clock before power goes up complicates things significantly.

    Thanks for patience

    Marek

  • 0 in reply to Marek Kvas
    TI__Mastermind 26035 points

    Hi Marek,

    I ask my team member internally. As long as the CLKOUT signal satisfy the clock signal requirement of the PHY you connected, it should be fine.

    If PHY power up before the clock being stable, all the block will turn on before the clock being stable. The PHY will reference the unstable clock signal which bring PHY to unknown stage. Therefore, clock need to be stable before the power up.

    --

    Regards,

    Hillman Lin