DP83826E: Please provide the definition of setup time/hold time/latch value (such as Vil of RST_N) of DP83826E HW strap pin

Jeffrey Fang

Prodigy 10 points

Part Number: DP83826E

Tool/software:

Hi,

Hardware Bootstraps pins are sampled at power up or hard reset.

We don’t know which point of VDDA3V3/RST_N (?) should be used to judge the strap value?

Please provide the definition of setup time/hold time/latch value(such as Vil of RST_N) of DP83826E HW strap pin.

(Including signals used by power up and hard reset to judge)

BR,

Jeffrey

over 1 year ago

0 Hillman Lin over 1 year ago

TI__Mastermind 25955 points

Hi Jeffrey,

The strapping event should take place before 50ms. T3 is the maximum timing for the latch up event to finish.

Regards,

Hillman lin

0 Jeffrey Fang over 1 year ago in reply to Hillman Lin

Prodigy 10 points

Hi Hillman,

Thank you for your reply,

So for power up, can I just look at the Voltage Ramp Duration of VDDA3V3, or should I look ahead 50ms to make sure that the strapping values are correct?

In addition, does hard reset confirm RESET_N? Is its judgment method the same?

BR,

Jeffrey

0 Hillman Lin over 1 year ago in reply to Jeffrey Fang

TI__Mastermind 25955 points

Hi Jeffrey,

Yes, you are correct.

Strapping occur during the POR time. Therefore we normally justify by T3 number.

Regards,

Hillman Lin

Interface

Interface forum

DP83826E: Please provide the definition of setup time/hold time/latch value (such as Vil of RST_N) of DP83826E HW strap pin