TCA9548A-Q1: Does the number of enabled gates affect the SCL rise time?

user6013811

Prodigy 170 points

Part Number: TCA9548A-Q1
Other Parts Discussed in Thread: TCA9548A

Tool/software:

Hello there,

In our design, we observed that the SCL rise time from the I2C Master to the TCA9548A-Q1 is not a fixed slope.

The measured minimum is 165ns, and the maximum is 288ns.

Is this because the different number of TCA9548A-Q1 output Ports enabled increases the capacitance (Ci)?

How do we calculate the input capacitance of SCL?

Thanks

Best regards,
Frank

over 1 year ago

0 Clemens Ladisch over 1 year ago

Guru 316640 points

Yes, all enabled channels are directly connected together, so their capacitances and pull-up resistors are visible on the main bus.

Just add up the capacitances (or pull-up currents) of all channels that can be enabled at the same time.

0 user6013811 over 1 year ago in reply to Clemens Ladisch

Prodigy 170 points

Hi Clemens,

Thank you for your reply.

Due to changes in the rise time, some of our frequencies exceed 400kHz (approximately 416kHz).

Does this violate the I2C fast mode specifications?

We saw that the MAX spec of the TMP422AQDCNRQ1 is 400kHz in fast mode.

Thanks

Best regards,
Frank

0 Clemens Ladisch over 1 year ago in reply to user6013811

Guru 316640 points

The frequency is derived from the interval between rising edges on the SCL line; the rise time must be fast enough (< 1 µs), but is otherwise unrelated.

0 user6013811 over 1 year ago in reply to Clemens Ladisch

Prodigy 170 points

Thank you for your explanation.

I understand that the frequency is derived from the rising edge of the I2C.

If the frequency between the rising edge and the next edge in an SCL waveform is greater than 400K (e.g., 406K or 416K or more), is this acceptable?

Regards,

Frank

0 Clemens Ladisch over 1 year ago in reply to user6013811

Guru 316640 points

It is likely to work, but the TCA9548A datasheet does not guarantee this.

0 user6013811 over 1 year ago in reply to Clemens Ladisch

Prodigy 170 points

I understand.

So it is inevitable that the I2C SCL frequency is affected by the rise time.

Do you recommend that we design the maximum frequency (when the chip switches to the minimum capacitance path which means minimum rise time) to be below 400 kHz (e.g. max: 400 kHz, min: 384 kHz) to ensure it is within specification?

Thanks

0 Clemens Ladisch over 1 year ago in reply to user6013811

Guru 316640 points

Yes, you should always keep inside the documented limits.

Is the I²C communication in your application time critical? The I²C protocol itself does not have a lower bound on the speed.

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TCA9548A-Q1: Does the number of enabled gates affect the SCL rise time?