• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 153 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65DSI86: Interfacing between low resolution processor with high resolution screen

Wei Xiao
Intellectual 425 points
Part Number: SN65DSI86

Tool/software:

One of the processors we are using supports MIPI DSI output at 2520*1080@60fps max. However, we are trying to use it with screens with higher resolutions. One example is a screen of 2880*1920@60hz with 4 lane edp input. Can SN65DSI86 be used for the application? If not, any other IC that may have scaling feature can be used in this case? Thank you.

  • 0
    TI__Guru**** 156181 points

    Hi,

    Please see this app note, https://www.ti.com/lit/an/slla425/slla425.pdf, in particular section 3 for the calculation. You have to calculate the stream bit rate, and from the stream bit rate, depending on the number of DSI lanes being used, you can't exceed the maximum 750MHz DSI clock.

    Do you know the pixel clock frequency for this particular resolution?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Intellectual 425 points

    Hi David,

    Thank you for the reply. I did some calculation and it seems that with the display panel spec, it requires more than 4 DSI lanes, which exceeds what the process can provide. Can we use a 1:2 MIPI DSI bridge with scaling to solve the problem? Please let me know if you have any recommendations. Thank you.

  • 0 in reply to Wei Xiao
    TI__Guru**** 156181 points

    Hi,

    Can you share your calculation? And are you calculating with 24bpp? I think with 18bpp, it is possible to support this design implementation of 4 DSI lanes.

    Unfortunately we do not have a 1:2 MIPI Bridge in our product portfolio.

    Thanks

    David 

  • 0 in reply to David (ASIC) Liu
    Intellectual 425 points

    Hi David,

    I am still getting detailed parameters of the display to make sure the calculation is correct. In the meantime, please help me with the following question. To support the screen of 2880*1920@60hz, do we need to config the MIPI DSI output of the processor to match the parameters? If yes, then the processor may not support the setting. When we tried the resolution setting, the device cannot even boot up. The maximum PCLK of MIPI DSI output support by the processor may be around 220Mhz. If that's the case, is DSI86 still an option to interface between the process and the screen of 2880*1920@60hz with four lane edp? Thank you.

  • 0 in reply to Wei Xiao
    TI__Mastermind 21285 points

    Hey Wei,

    The DSI86 is unable to pad the signal coming from the source so it will not be able to increase the resolution from 2520*1080@60fps to 2880*1920@60hz. This DSI86 is a simple bridge which converts a MIPI DSI signal to an eDP signal, it is unable to alter the output resolution. The input and output resolution must be matched up.

    The approx. pixel clock needed for the high resolution screen is

    Htotal * Vtotal * RR = (2880*1.3) * (1920 *1.3) * 60 =  560,701,440 which is within 750MHz so it should work for single channel mode.