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DP83822I: How to detect a fault

Part Number: DP83822I

Tool/software:

We are considering a function that would reference register values ​​at startup or at any time after startup to detect hardware failures on the device itself.
Additionally we are considering features that will detect failures other than hardware failures.

1)

When a hardware failure is detected in an Ethernet PHY register, is there a register that can identify that a failure has occurred and the type of failure that has occurred?
Also, if you need to check multiple registers to isolate the fault, please tell us which ones they are.

2)

Are there any registers in the Ethernet PHY that can identify the occurrence of a fault during operation other than a hardware fault, and the type of fault that has occurred?
Also, if it is necessary to check multiple registers to identify the fault, please tell me which registers they are.

3)

What are the conditions under which the bits of these registers are set?
    ANER
        BIT4 Parallel Detection Fault
          「A fault has been detected during the parallel detection process」
            Under what conditions does this failure occur?

    PHYSTSレジスタ
        BIT13 Receive Error Latch
        BIT11 False Carrier Sense Latch
        BIT6 Remote Fault
        BIT5 Jabber Detect
            Under what conditions is this detected?

4)

What external factors or actions cause these registers to be set?

Please answer in the order that you can.

  • Hi Hiroki,

    Thank you for submitting your question, please find my reply below.

    1.  There are several interrupt registers that can be monitored for various faults/changes. Please see Reg 0x12 - 0x15 
    2.  same as 1. 
    3.  Parallel detection is a mechanism used by auto-negotiation. In the event that the PHY (with autoneg enabled) is connected to a link partner that has auto-negotiation disabled, this is supposed to help find the correct link speed. More information regarding this feature is well documented online.
      1. All of these are well documented online, this forum is meant more for functional issues, are you seeing anything wrong at the moment?
    4. same as 3

    Regards,

    Alvaro

  • Thank you for your answer. I have an additional question.

    1)

    > Parallel detection is a mechanism used by auto-negotiation. In the event that the PHY (with autoneg enabled) is connected to a link partner that has auto-negotiation disabled, this is supposed to help find the correct link speed. More information regarding this feature is well documented online.

    Can you tell me the URL here?

    2)

    I am currently working on a program that monitors for the occurrence of False Carrier Sense Latch.

    I set the following registers to set the speed and auto-negotiation:
        ・BMCR
        ・ANAR

    After I set this register, can I get the exact occurrence status of "False Carrier Sense Latch" at any time in the following cases?
         Case1 The register was set with the LAN cable connected.
         Case2 After setting up the register, I connected the LAN cable.

    3)

    If the answer to the second question is "no", please answer.

    After setting the register, what condition should I wait for?

  • Hi Hiroki,

    Alvaro is Out of Office today. He will reach back to you by the early next week.

    --

    Sincerely,

    Hillman Lin

  • Hi Hiroki!

    Thank you for your patience.

    More on parallel detection can be found here: Auto_Negotiation_Process_1.pdf 

    For False Carrier Sense, the best way would be to use an interrupt.

    • Reg 0x11, Bit[1] must be set high to enable event based interrupts.
    • Reg 0x12, Bit[1] must be set high to enable False Carrier Half/Full interrupt
      • Now Bit[9] will go high when half full (counter = 7Fh) and when full (counter = FFh)
    • Reg 0x14, Bits[7:0] will keep count of false carrier events
      • This register will be cleared each time you read it

    You can check this register at any time, regardless if the cable is plugged in or not.

    Regards,

    Alvaro