Tool/software:
Team-
The datasheet for the '935 shows the following bypass networks:
To meet final end customer requirements, the designer needs to document that their implementation provides the minimum necessary capacitance on each bypass section:
what is the minimum capacitance needed on the VDD rails after taking into account the following:
- DC Bias Derating
- Aging
- Temperature
- Tolerance (initial)
WCCA has been an activity that was placed on us by our end customer. They have stated the following rules for WCCA:
- MLCC Caps are derated as follows:
- Initial Tolerance
- Aging
- DC Bias
- Temperature Derating
- Equation is then Eff Cap = Value*(1-init_tol)*(1-aging)*(1-dc_bias)*(1-temp) ***Note: TI uses this exact equation when computing eff cap for the PoC filter of FPD-Link capacitance
- You then add up all that capacitance as seen below and compare it to the “minimum capacitance” value provided by the vendor
- Here is the catch though… 99% of vendors don’t have a “minimum capacitance” to give you – they just have recommended cap values on app notes, datasheets, or eval cards
In order to show that the design is meeting TI's requirements, we need to know what the minimum total capacitance after derating on the bypassed pins is required.
Can you please provide a number here? By the looks of it, (see note above) TI is already doing this for the PoC filter capacitance.
Thanks!
-Steve
