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DP83867E: RBIAS resistor value for ethernet compliance test

Part Number: DP83867E

Tool/software:

Hi, Expert

Data sheet recommend RBIAS resistor value should be 11kΩ. I think this value works fine (11kΩ) on customized board, but got failed for ethernet compliance test.

Customer try to reduce RBIAS resistor to 8kΩ, and then ethernet compliance test pass.

we also try to adjust Gain Register (PROG_GAIN), Reg 0x1D5 = 0xF508 with  RBIAS resistor 11kΩ, and it also gets fail for ethernet compliance test. (Sets required swing level for compliance testing)

My question.

(1) What's resistor value range for RBIAS?

(2) Do it have any side effect to reduce RBIAS resistor value? because I am not sure it is a normal workaround way.

(3) What's mean to reduce RBIAS resistor? Does it have any defect on customer's board design?

I already reference this thread.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1360848/am6422-rbias-resistor-value-for-dp83867irrgz/5191907?tisearch=e2e-sitesearch&keymatch=RBIAS%20resistor#5191907

I feel confuse, because most of user case try to modify RBIAS resistor to 10kΩ is sufficient

Many Thanks

Gibbs

  • Hi Gibbs,

    Please share which compliance test is failing, and the margins of failure.

    If possible, please send test report. Datasheet value for RBIAS is recommended, I would like to focus on debug relative to schematic, layout, and compliance script checks.

    Thank you,

    Evan

  • Hi, Evan

    Status update from customer.

    They set RBIAS resistor value return to 11kΩ, and adjust these register. (ANA_LD_TXG_FINE_GAINSEL_AB/ANA_LD_TXG_FINE_GAINSEL_CD/ANA_LD_FILTER_TUNE_AB/ANA_LD_FILTER_TUNE_CD)

    0x00A0=0x0707, 0x00A1=0x0707, 0x00A2=0x2f2f, 0x00A3=0x2f2f

    Base on this setting, they pass 1G compliance test, but failed for 100Mbps.

    Does it mean we should read BMCR register first, software try to identify PHY works in 1G or 100Mbps, and then give different register settings sets to match 

    compliance test?

    If customer get template test failed, how to solve this problems? Do we have any register setting about template test?

    By the way, If you need relative schematic, layout, and compliance script, May I mail to you directly?

    Many Thanks

    Gibbs

  • Hi Gibbs,

    Thanks for confirming the working register sequence for 1G.

    Does it mean we should read BMCR register first, software try to identify PHY works in 1G or 100Mbps, and then give different register settings sets to match 

    compliance test?

    Yes, this is an acceptable workaround to pass compliance for the time being. I would like to focus on schematic/layout/compliance script checks to see if there are any optimizations we can make to have compliance pass without additional register changes.

    Regarding template test, please share more details about the customer results.

    Project files & compliance report can be sent to e-mayhew@ti.com , I will review.

    Thank you,

    Evan

  • Hi, Evan

    Status update, problem solved for 100Mbps.

    But customer feedback (guess), datasheet should be have some context error.

    ANA_LD_FILTER_TUNE_AB is for channel C & D

    ANA_LD_FILTER_TUNE_CD is for channel A & B

    Need you internal confirm.

    Many Thanks

    Gibbs

  • Hi Gibbs,

    Is mirror mode or auto-MDIX enabled in the customer's application? This may re-order the channels and cause confusion with channel-based register tuning.

    Thank you,

    Evan

  • Hi, Evan

    Already sent some information to your mail.

    May you help me check it?

    Thank You.

    Gibbs

  • Hi Gibbs,

    Yes, please expect feedback by tomorrow at the latest.

    Thank you,

    Evan

  • Hi Gibbs,

    I am closing this thread as we have moved to email for debug.

    Thank you,

    Evan