DP83867IR: What is the min max values Internal pullup and pulldown resistors

Hi William,

Inputs are expected to be high-Z during normal operation.

Internal PU / PD resistors are ~9k +/- 30%, but this impedance is only seen during strapping stage on power-up.

Can you please clarify the issue or confusion here?

Thank you,

Evan

We plan to drive the RESET_N pin of the DP83867IR from a GPIO pin of a processor (LS1028A). At power up there is a delay before the processor configures the GPIO pin to drive the DP83867IR RESET_N pin. Therefore, an external pulldown resistor will be added to hold the DP83867IR in reset until the processor GPIO output becomes active. The minimum / maximum value of this added resistor will depend on the internal pullup resistor value within in the DP83867IR 

Thanks for clarifying. Please assume 9k for this pin.

Thanks. Do you have a tolerance for the 9K resistor value or any characteristic data for value over temperature?

9k +/- 30% is the information I have available.

V(IL) = 0.7V for RESET_N (VDDIO=3.3/2.5V) - there is some flexibility in the PD chosen before exceeding VIL.

Thank you,

Evan