DP83TC813S-Q1: Ask about the delay time

Jack Li

Intellectual 1650 points

Part Number: DP83TC813S-Q1
Other Parts Discussed in Thread: TDA2

Tool/software:

Hi PHY team,

May you have a good day! My customer meet with a question, please help to give a reply:

Hardware Background: They use SOC: TDA2S +PHY Chip: DP83TC813S;

Software configuration: SOC side RGMII interface (RX and TX are configured for align mode), PHY: DP83TC813S (RX is delay mode, TX is configured for align mode);
Problem: Frames are dropped when the computer is connected to the light transfer.
Workaround: Resolve by modifying the 602 register bit 0 = 1 on the PHY side, as follows:

They have two questions:

Question 1: Please help to provide the timing diagram of the SOC-side (TDA2S) align mode, which can be matched with the phy-side (delay) mode;
Question 2: The SOC side defaults to delay mode in the manual, which is based on whether the SOC is delay mode, the PHY must be align mode. Timing is as below:

Best Regards,

Jack

3 months ago

0 Melissa Chang 3 months ago

TI__Genius 11140 points

Hi Jack,

Jack Li said:
Question 1: Please help to provide the timing diagram of the SOC-side (TDA2S) align mode, which can be matched with the phy-side (delay) mode;

Please reach out to the processor team for questions related to the TDA2S.

Jack Li said:
Question 2: The SOC side defaults to delay mode in the manual, which is based on whether the SOC is delay mode, the PHY must be align mode. Timing is as below:

If you are asking why programming the delay works for your setup, the RGMII delay can be affected by the layout aswell. It is normal to have to do this type of adjustment during board bring up, there should be no risk.

Best regards,

Melissa

0 Andy Ye 3 months ago in reply to Melissa Chang

TI__Prodigy 120 points

Hi Melissa,

Below is currently RGMII TX timing configuration are works well for their current design

In TDA2 datasheet shows RGMII TX signal internal delay is always enabled (can't set to align mode)
based on theoretically, they previously set 813 TX into align mode, but it shows packet loss issue
Now 813 TX setting to delay mode, 0x602[0] = 1, no packet loss issue, it works well

customer concerns are below:

SOC TX delay + PHY TX delay ==> may cause overall TX delay over range for PHY receiving
What is PHY TX delay mode requirement of Tset_up/Thold, need provide timing diagram and parameter requirement
they need us to give them those parameters, then to create report to OEM make sure the current setting is reliable.

0 Melissa Chang 3 months ago in reply to Andy Ye

TI__Genius 11140 points

Hi Andy,

Andy Ye said:
What is PHY TX delay mode requirement of Tset_up/Thold, need provide timing diagram and parameter requirement

This can be found in section 7.6 and 7.7 of the datasheet.

Here is the timing requirements, diagram is in section 7.7. For PHY RGMII input, there is a 1ns minimum requirement.

Andy Ye said:
SOC TX delay + PHY TX delay ==> may cause overall TX delay over range for PHY receiving

Andy Ye said:

they need us to give them those parameters, then to create report to OEM make sure the current setting is reliable.

1. In 100Mbps, RGMII has a clock signal of 25 MHz (40 ns period).

When you program shift mode in the PHY, it adds a delay of 2ns (a small fraction of 40ns).

Can you check the RGMII delay of TDA2? If it also around 2ns, the total delay would 4ns. With the clock signal being 40ns, there is still plenty of margin.

2. Since layout is a factor, we do not know the exact delay until we can take a measurement of their design.

If they can take a scope shot of their RGMII signals (zoomed into the ~4ns/div) triggered on the rising edge of the CLK and data, we should be able to prove to the OEM that there is still a lot of margin left.

Best regards,

Melissa

Interface

Interface forum

DP83TC813S-Q1: Ask about the delay time