TCAN4550-Q1: The canfd transmitter can only normally send 28 frames at a time

set TXESC.TBDS=0b111, 64 bytes/elements.

write 32 frames * 64 bytes to tx buffers.

Hello Apologize,

Did you by chance enable any dedicated TX Buffers as well?  There is a total of 32 TX buffers and it is possible to have a combination of dedicated TX Buffers and a TX Queue and I am wondering if there is a conflict in the configuration. 

Can you tell me what the value of the TX Buffer Configuration (TXBC) register address 0x10C0 is?

Can you monitor the following TX related registers:

• TX FIFO/Queue Status (TXFQS) register address 0x10C4
• TX Buffer Request Pending (TXBRP) register address 0x10CC
• TX Buffer Transmission Occurred (TXBTO) register address 0x10D8

Regards,

Jonathan

TXBC.TFQM=0,TXBC.TFQS=0,TXBC.NDTB=32,TXBC.TBSA=0x8000+1*4+32*(64+8)

I found that when I finish writing 64 bytes of data and 8 bytes of headers for frames 0 to 27,

and 8 bytes of headers and 24 bytes of data(32 bytes in total) for frame 28 ,

the above total 28*(8+64)+32=32*64 bytes.

and the remaining 40 bytes of frame 28  covered the MRAM of frame 0,

the header and datas for frame 29 covered the mram of frame 0 and frame 1,

the header and datas for frame 30 covered the mram of frame 1 and frame 2,

the header and datas for frame 31 covered the mram of frame 2 and frame 3.

So the cause of the error semms to be  that the mram area of the first 4 frames is overwritten.

I also wonder if RX FIFO 0 can store 32*(8+64)bytes of messages at once. In my test, the last 4 frames（8+64 bytes） will overwrite the first 4 frames, which means that the maximum storage space of RX FIFO  0 is 32*64 bytes. And RX FIFO 0 and RX FIFO 1 share the 32*64 bytes

There is only 2kB of MRAM occupying address 0x8000 to 0x87FF for all of the different memory elements.  It is not possible to allocate the maximum number of elements supported by MCAN, so you will need to determine what your application needs and ensure it fits within the MRAM without overlapping addresses. 

If your configuration exceeds 2kB, the memory cycles back to the beginning of the address space.  For example, if you attempt to read or write from address 0x8800, this is the same as a read or write to 0x8000.

32 TX Buffer elements with the maximum data size of 64 bytes is a total of 2304 bytes, which is greater than the MRAM block size of 2000 bytes.  You will need to reduce the number of TX Buffer elements, or the data size of the buffer elements in order to stay below 2kB and prevent overwriting some of your TX buffer elements.

Regards,

Jonathan

Yes, I just realized it yesterday. Thanks