Tool/software:
SCHEMATIC1 _ 07_CAN_IOT_motor.pdf
Hi team,
Could you help to review the SCH as the attachment? any suggestions pls let me know.
BR
Jingguo
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Tool/software:
SCHEMATIC1 _ 07_CAN_IOT_motor.pdf
Hi team,
Could you help to review the SCH as the attachment? any suggestions pls let me know.
BR
Jingguo
Hi Jingguo,
I have reviewed the schematic and I have the following comments.
If a single-ended clock is used on the OSC1 pin instead of a crystal, the OSC2 pin will need to be connected to GND. I would suggest adding a 0-ohm resistor to GND option on OSC2 pin that would allow OSC2 pin to be "Grounded" when the single-ended clock is used.
I would also recommend placing a 0-ohm resistor between the OSC1 pin and the Crystal that can used to isolate the crystal from the single-ended clock so that it does not try to start oscillating when the single-ended clock is used. This resistor will also be needed when optimizing the crystal circuit when the crystal is used instead of a single-ended clock.
Please review the TCAN455x Clock Optimization and Design Guidelines Application Note (Link).
The FLTR pin requires a minimum capacitance of 300nF to ensure stability of LDO used to run the digital core. A 330nF capacitor is commonly used on the FLTR pin instead of the 100nF shown in the schematic.
The nINT pin is an open-drain pin that requires an external pull-up resistor to VIO.
Regards,
Jonathan