DP83867IR: Loading on the TX_D0 & TX_D1 is higher than TX_CLK, TX_D2 & TX_D3

Hello,

We are looking into this at the moment; please expect an update by end of week at latest.

Sincerely,

Gerome

Dear TI Team, 

Below is additional question i have, Could you help me to get below information? this help me to understand this my test observation & issue. 

-> How TI confirm input high/low current will not go above the limit specified in datasheet of DP83867IRRGZ ? Production test or design? 

-> How TI confirm input capacitance not go above the limit specified in the datasheet of DP83867IRRGZ ? Production test or design? 

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Vaibhav

Hi Vaibhav,

I am working with Sreenivasa in your connected thread and in efforts to consolidate conversation, will look to continue debug through that thread.

Regarding your new question, I cannot reveal that data as test methodology is proprietary information to TI.

Sincerely,

Gerome

Dear Gerome,

If you not share the data then how we can trust on the reliability of DP83867IRRGZ? if you have any concern on the sharing data on the e2e platform then you can provide me data on my email. 

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Vaibhav

Dear Gerome,

Gerome Cacho said:

If you see that your design is not meeting these specifications, then we can have a further conversation as to why that is the case.

Relay we don't request such an information if our design meet the datasheet specification, but this is not the case for now.

Can you please give a specific timeline, by when you (TI) will able to resolve the problem/provide the solution?

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Vaibhav

Hi Vaibhav,

I cannot comment on a specific timeline as the debug is still ongoing, but I can provide a next check-in update of next Monday. US offices will be going on Holiday on Thursday, with some extending into the long weekend.

Again, for consolidation purposes, we will look to continue on the aforementioned thread.

Sincerely,

Gerome