DP83TC812S-Q1: question about the RGMII signaling behavior

Hi Jiahua,

Let me check with the team on this. Due to U.S. holiday, I will get back by early next week.

Thanks,

David

Hi Jiahua,

The DP83TC812 does not support EEE, please leave this register as default value. 

Thanks,

David

Hi David

    So the configuration of this register will not take any effect? There is still a lpi_exit signal in my rx data. I wanna know if the lpi_exit signaling exist and can be changed by software configuration.

Thanks

Hi Jiahua,

Can you please share how you are seeing a lpi_exit signal? This is using wireshark? Please share screenshot if possible.

Is normal data throughput successful?

Is EEE enabled on the link partner?

Thanks,

David

I caught the RXCLK,RXCTL and RXDATA0 on the RGMII line between PHY and MAC, and saw the rxdata0 was 0 and RXCTL was up at  falling edge. It matches the lpi_exit signal description, but I am unsure whether it is. It is inconsistent with the format of sfd, so MAC parses the received data abnormally and thinks that a phy error has occurred.

Hi Jiahua,

Does this happen with every single packet that is sent? Does MAC think that 100% of packets have errors?

Please read PHY register 0x15, 0x63C, 0x63D, 0x63E and share the values.

Thanks,

David

Yes, even if a number of frames are sent to the MAC in succession, this phy error is reported for each frame. Regarding the values of the registers you asked about, Reg 0x15,0x63d and 0x63e always remain at 0, Reg 0x63c changes with the number of received messages, which indicates that there are no error packets.

I think the problem is that d0 always goes low at the beginning, but this should stay at 1 accoding to the header format. Is it possible that though eee is not supported, a signaling behavior similar to lpi_exit still exists?

Dear David,

     I did a simple initialization based on datasheet only with the following steps:

1)write 0x8100 to Reg0 , and wait for soft-reset completes

2)write 0x2100 to Reg0, work on 100M full duplex mode

3)write 0x02 to Reg 0x602, MMD1F,  for rx shift mode

     I'm in fpga-based simulation and not using linux OS. I modified my initialization according to your script above, and found that cross-board communication no longer reports errors, although the phy digital loopback is still problematic. The script configures a number of registers, which are not mentioned in the datasheet, so I didn't understand why it stopped reporting errors, and I'm still trying to get my head around the problem and the exact configuration that took effect. So far it seems to be a problem with my default hardware configuration. The script helps me a lot. Here's still giving the register values you mentioned

Thanks,

J.M

Hi Jiahua,

Glad to hear the cross-board communication no longer reports errors.

When you say that digital loopback is still problematic, what does this mean? Do other loopbacks (PCS, Analog) have the same problem? Can you share the register configuration you are using to enable loopbacks?

Thanks,

David